NT512D64S8HA0G-75B Просмотр технического описания (PDF) - Nanya Technology
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NT512D64S8HA0G-75B Datasheet PDF : 14 Pages
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NT512D64S8HAAG
512MB : 64M x 64
PC2100 / PC1600 Unbuffered DIMM
Serial Presence Detect -- Part 1 of 2
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
SPD Entry Value
Description
DDR266A DDR266B DDR200
-7K
-75B
-8B
Number of Serial PD Bytes Written during
128
Production
Total Number of Bytes in Serial PD device
256
Fundamental Memory Type
SDRAM DDR
Number of Row Addresses on Assembly
13
Number of Column Addresses on Assembly
10
Number of DIMM Bank
2
Data Width of Assembly
X64
Data Width of Assembly (cont’)
X64
Voltage Interface Level of this Assembly
SSTL 2.5V
DDR SDRAM Device Cycle Time at CL=2.5
7ns
7.5ns
8ns
DDR SDRAM Device Access Time from
Clock at CL=2.5
0.75ns 0.75ns
0.8ns
DIMM Configuration Type
Non-Parity
Refresh Rate/Type
SR/1x(7.8us)
Primary DDR SDRAM Width
X8
Error Checking DDR SDRAM Device Width
N/A
DDR SDRAM Device Attr: Min CLk Delay,
Random Col Access
1 Clock
DDR SDRAM Device Attributes:
Burst Length Supported
2,4,8
DDR SDRAM Device Attributes: Number of
4
Device Banks
DDR SDRAM Device Attributes: CAS
Latencies Supported
2/2.5
2/2.5
2/2.5
DDR SDRAM Device Attributes: CS Latency
0
DDR SDRAM Device Attributes: WE Latency
1
DDR SDRAM Device Attributes:
Differential Clock
DDR SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
Minimum Clock Cycle at CL=2
7.5ns
10ns
10ns
Maximum Data Access Time from Clock at
CL=2
0.75ns
0.75ns
0.8ns
Minimum Clock Cycle Time at CL=1
N/A
Maximum Data Access Time from Clock at
N/A
CL=1
Minimum Row Precharge Time (tRP)
20ns
20ns
20ns
Minimum Row Active to Row Active delay
(tRRD)
15ns
15ns
15ns
Minimum RAS to CAS delay (tRCD)
20ns
20ns
20ns
Minimum RAS Pulse Width (tRAS)
45ns
45ns
50ns
Module Bank Density
256MB
Address and Command Setup Time Before
Clock
0.9ns
0.9ns
1.1ns
Address and Command Hold Time After
Clock
0.9ns
0.9ns
1.1ns
Data Input Setup Time Before Clock
0.5ns
0.5ns
0.6ns
Data Input Hold Time After Clock
0.5ns
0.5ns
0.6ns
Reserved
Undefined
SPD Revision
Initial
Initial
Initial
Checksum Data
Serial PD Data Entry (Hexadecimal) Note
DDR266A DDR266B DDR200
-7K
-75
-8B
80
08
07
0D
0A
02
40
00
04
70
75
80
75
75
80
00
82
08
00
01
0E
04
0C
0C
0C
01
02
20
00
75
A0
A0
75
75
80
00
00
50
50
50
3C
3C
3C
50
50
50
2D
2D
32
40
90
90
B0
90
90
B0
50
50
60
50
50
60
00
00
00
00
90
C0
46
REV 1.0 06 / 2002
5
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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