FM27C256 Просмотр технического описания (PDF) - Fairchild Semiconductor
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производитель
FM27C256 Datasheet PDF : 10 Pages
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AC Test Conditions
Output Load
1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times
≤ 5 ns
Input Pulse Levels
0.45 to 2.4V
Timing Measurement Reference Level (Note 10)
Inputs
0.8V and 2.0V
Outputs
0.8V and 2.0V
AC Waveforms (Note 6) (Note 7) (Note 9)
ADDRESSES 2.0V
0.8V
ADDRESSES VALID
CE 2.0V
0.8V
OE 2.0V
0.8V
OUTPUT 2.0V
0.8V
tCE
Hi-Z
tOE
(Note 3)
tACC
(Note 3)
VALID OUTPUT
tCE
(Notes 4, 5)
tDF
(Notes 4, 5)
Hi-Z
tOH
DS800034-4
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.
Note 4: The tDF and tCF compare level is determined as follows:
High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;
Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE.
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between VCC and GND.
Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.
Note 8: TTL Gate: IOL = 1.6 mA, IOH = -400 µA.
CL = 100 pF includes fixture capacitance.
Note 9: VPP may be connected to VCC except during programming.
Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 11: CMOS inputs: VIL = GND ±0.3V, VIH = VCC ±0.3V.
FM27C256
4
www.fairchildsemi.com
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