CY7C1352-143AC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1352-143AC Datasheet PDF : 12 Pages
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CY7C1352
Pin Definitions
Pin Number
80, 50−44,
81−82, 99−
100, 32−37
94, 93
Name
A[17:0]
BWS[1:0]
88
WE
85
ADV/LD
89
CLK
98
CE1
97
CE2
92
CE3
86
OE
87
CEN
23−22, 19−18,
13−12, 9−8,
73−72, 69−68,
63−62, 59−58
DQ[15:0]
24, 74
31
DP[1:0]
MODE
15, 16, 41, 65,
66, 91
4, 11, 14, 20,
27, 54, 61, 70,
77
5, 10, 17, 21,
26, 40, 55, 60,
64, 67, 71, 76,
90
VDD
VDDQ
VSS
I/O
Input-
Synchronous
Description
Address Inputs used to select one of the 262,144 address locations. Sampled at
the rising edge of the CLK.
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
I/O-
Synchronous
I/O-
Synchronous
Input
Strap pin
Power Supply
I/O Power
Supply
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS0 controls DQ[7:0] and DP0,
BWS1 controls DQ[15:8] and DP1. See Write Cycle Description table for details.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is
active LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an ac-
cess. After being deselected, ADV/LD should be driven LOW in order to load a
new address.
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device.
Chip Enable 2 Input active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside
the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated,
and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A[16:0] during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ[15:0] are placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ[15:0]. During write sequences, DP0 is controlled by BWS0 and DP1 is con-
trolled by BWS1
Mode input. Selects the burst order of the device. Tied HIGH selects the inter-
leaved burst order. Pulled LOW selects the linear burst order. MODE should not
change states during operation. When left floating, MODE will default HIGH to an
interleaved burst order.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
Ground
Ground for the device. Should be connected to ground of the system.
3
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