CY7C1352-143AC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1352-143AC Datasheet PDF : 12 Pages
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Switching Waveforms (continued)
Burst Sequences
CY7C1352
CLK
tALS
tALH
ADV/LD
tCH tCL
tCYC
ADDRESS RA1
tAS tAH
WA2
RA3
WE
tWS tWH
BWS[1:0]
tWS tWH
tCES tCEH
CE
tCLZ
tDOH
tCHZ
tDH
tCLZ
Data-
In/Out
Device
OQu11t a
Q1+1
Out
Q1+2 Q1+3
Out Out
D2
D2+1 D2+2 D2+3
Q3
In
In
In
In
Out
originally
deselected tCO
tCO
tDS
The combination of WE & BWS[1:0] defines a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[1:0] input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
= DON’T CARE
= UNDEFINED
10
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