AS5SS256K36 Просмотр технического описания (PDF) - Austin Semiconductor

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AS5SS256K36

256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM

Austin Semiconductor 

Austin Semiconductor, Inc.

SSRAM

AS5SS256K36 &

AS5SS256K36A

AC TEST CONDITIONS

Input Pulse Levels..................VIH = (VDD/2.2) +1.5V

..................VIL = (VDD/2.2) -1.5V

Input rise and fall times..........................................1ns

Input timing reference levels............................V /2.2

DD

Output reference levels................................VDDQ/2.2

Output load.................................See Figures 1 and 2

OUTPUT LOADS

DQ

Z0=50Ω

50Ω

DQ

351Ω

+3.3v

317Ω

5 pF

Vt = 1.5V

Fig. 1 3.3V I/O OUTPUT LOAD EQUIVALENT Fig. 2 3.3V I/O OUTPUT LOAD EQUIVALENT

NOTE: SRAM timing is dependent upon the capacitive loading on the outputs.

AS5SS256K36 &

AS5SS256K36A

Rev. 3.6 06/05

10

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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