CY7C1366A-225AJC Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1366A-225AJC Datasheet PDF : 27 Pages
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CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
512K X 18 Pin Descriptions (continued)
X18 PBGA Pins X18 QFP Pins Name
Type
Description
2B
97
CE2
Input-
Chip Enable: This active HIGH input is used to enable the
Synchronous device.
(not available for
PBGA)
92 (for TA Ver-
sion only)
CE2
Input-
Chip Enable: This active LOW input is used to enable the de-
Synchronous vice. Not available for B and T package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
4G
83
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
84
ADSP
Input-
Address Status Processor: This active LOW input, along with
Synchronous CE being LOW, causes a new external address to be registered
and a Read cycle is initiated using the new address.
4B
85
ADSC
Input-
Address Status Controller: This active LOW input causes de-
Synchronous vice to be deselected or selected along with new external ad-
dress to be registered. A Read or Write cycle is initiated de-
pending upon write control inputs.
3R
31
MODE
Input-
Mode: This input selects the burst sequence. A LOW on this
Static
pin selects Linear Burst. A NC or HIGH on this pin selects
Interlinear Burst.
7T
64
ZZ
Input-
Snooze: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
(a) 6D, 7E, 6F, 7G, (a) 58, 59, 62, 63,
6H, 7K, 6L, 6N, 7P 68, 69, 72, 73, 74
(b) 1D, 2E, 2G, 1H, (b) 8, 9, 12, 13,
2K, 1L, 2M, 1N, 2P 18, 19, 22, 23, 24
DQa
DQb
Input/
Output
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb. Input
data must meet set up and hold times around the rising edge
of CLK.
2U
38
TMS
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. Not available for
3U
39
TDI
TA package version.
4U
43
TCK
for B and T
version
5U
42
TDO
Output IEEE 1149.1 test output. LVTTL-level output. Not available for
for B and T
TA package version.
version
4C, 2J, 4J, 6J, 4R 15, 41,65, 91 VCC
3D, 5D, 3E, 5E, 3F, 5, 10, 17, 21, 26, VSS
5F, 5G, 3H, 5H, 3K, 40, 55, 60, 67,
5K, 3L, 3M, 5M,
71, 76, 90
3N, 5N, 3P, 5P
Supply
Ground
Core power Supply: +3.3V –5% and +10%
Ground: GND.
1A, 7A, 1F, 7F, 1J, 4, 11, 20, 27, 54, VCCQ
7J, 1M, 7M, 1U, 7U 61, 70, 77
I/O Supply Output Buffer Supply: +2.5V or +3.3V.
1B, 7B, 1C, 7C, 2D, 1-3, 6, 7, 14, 16, NC
4D, 7D, 1E, 6E, 2F, 25, 28-30, 51-53,
1G, 6G, 2H, 7H, 56, 57, 66, 75,
3J, 5J, 1K, 6K, 2L, 78, 79, 80, 95, 96
4L, 7L, 6M, 2N, 7N,
1P, 6P, 1R, 5R, 7R, 38, 39, 42 for TA
1T, 4T, 6U
Version
-
No Connect: These signals are not internally connected. User
can leave it floating or connect it to VCC or VSS.
7
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