AS5SS256K18 Просмотр технического описания (PDF) - Austin Semiconductor
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AS5SS256K18 Datasheet PDF : 13 Pages
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Austin Semiconductor, Inc.
SSRAM
AS5SS256K18
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) -55oC < TA < +125oC and -40oC<TA<+85oC; VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
CLOCK
DESCRIPTION
SYMBOL
-8
MIN MAX
-9
MIN MAX
-10
MIN MAX
UNITS
NOTES
Clock cycle time
tKC
8.8
10
15
ns
Clock frequency
tKF
113
100
66
MHz
Clock HIGH time
tKH
2.5
3.0
4.0
ns
2
Clock LOW time
OUTPUT TIMES
tKL
2.5
3.0
4.0
ns
2
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
tKQ
7.5
8.5
10
tKQX
1.5
3.0
3.0
tKQLZ
1.5
3.0
3.0
ns
ns
3
ns 3, 4, 5
Clock to output in High-Z
OE\ to output valid
OE\ to output in Low-Z
tKQHZ
tOEQ
tOELZ
4.2
5.0
4.2
5.0
0
0
0
5.0
ns
3, 4, 5
5.0
ns
6
ns 3, 4, 5
OE\ to output in High-Z
SETUP TIMES
tOEHZ
4.2
5.0
5.0
ns
3, 4, 5
Address
Address status (ADSC\, ADSP\)
Address advance (ADV\)
Byte write enables (BWa\-BWb\, GW\, BWE\)
Data-in
tAS
1.5
1.8
2.0
tADSS
1.5
1.8
2.0
tAAS
1.5
1.8
2.0
tWS
1.5
1.8
2.0
tDS
1.5
1.8
2.0
ns
7, 8
ns
7, 8
ns
7, 8
ns
7, 8
ns
7, 8
Chip enable (CE\)
HOLD TIMES
tCES
1.5
1.8
2.0
ns
7, 8
Address
Address status (ADSC\, ADSP\)
Address advance (ADV\)
tAH
0.5
0.5
0.5
tADSH
0.5
0.5
0.5
tAAH
0.5
0.5
0.5
ns
7, 8
ns
7, 8
ns
7, 8
Byte write enables (BWa\-BWb\, GW\, BWE\)
Data-in
Chip enable (CE\)
tWH
0.5
0.5
0.5
tDH
0.5
0.5
0.5
tCEH
0.5
0.5
0.5
ns
7, 8
ns
7, 8
ns
7, 8
NOTES:
1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V +0.3V/-0.165V) unless otherwise
noted.
2. Measured as HIGH above V and LOW below V .
IH
IL
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. OE\ is a “Don’t Care” when a byte write enable is sampled LOW.
7. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is
defined by at least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times.
8. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\ or
ADSC\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges
of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is LOW to
remain enabled.
AS5SS256K18
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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