ALC250 Просмотр технического описания (PDF) - Unspecified
Номер в каталоге
Компоненты Описание
производитель
ALC250 Datasheet PDF : 46 Pages
| |||
ALC250 Data Sheet
If DRA = 1, DAC operates at a fixed 96KHz sampling rate. The PCM(n) and PCM(n+1) data is captured in the
same frame. In this mode, MX2C is fixed at BB80h, MX32 and ADC is still controlled by VRA.
SPCV is a read only bit that indicates whether the current S/PDIF-Out configuration is supported or not. If the
configuration is supported, SPCV is set as 1 by H/W. So driver can check this bit to determine the status of the
S/PDIF transmitter system. SPCV is always operating, independent of the SPDIF enable bit (MX2A.2). The
S/PDIF output is active if MX2A.2 is set in spite of SPCV. Once S/PDIF output is enabled but SPCV is invalid
(SPCV=0), channel status is still output, but the output data bits will be all zero.
6.1.21 MX2C PCM DAC Rate
Default: BB80h
The ALC250 allows adjustment of the output sample rate. This register is used to adjust the sample rate. By changing the values,
sampling rates from 8000 to 48000 can be chosen.
Bit Type
Function
15:0 R/W Output Sampling Rate FOSR[15:0]
The ALC250 supports the following sampling rates, as required in the PC99/PC2001 design guide.
Sampling rate
FOSR[15:0]
8000
1F40h
11025
2B11h
12000
2EE0
16000
3E80h
22050
5622h
24000
5DC0
32000
7D00h
44100
AC44h
48000
BB80h
Note that If the value written is not support, the closest value is returned.
When MX2A.0=0 (VRA is disable), this register will return BB80h when read.
6.1.22 MX32 PCM ADC Rate
Default: BB80h
The ALC250 allows adjustment of the input sample rate. This register is used to adjust the sample rate. By changing the values,
sampling rates from 8000 to 48000 can be chosen.
Bit Type
Function
15:0 R/W Output Sampling Rate FISR[15:0]
The ALC250 supports the following sampling rates, as required in the PC99/PC2001 design guide.
Sampling rate
FISR[15:0]
8000
1F40h
11025
2B11h
12000
2EE0
16000
3E80h
22050
5622h
24000
5DC0
32000
7D00h
44100
AC44h
48000
BB80h
Note that If the value written is not support, the closest value is returned.
When MX2A.0=0 (VRA is disable), this register will return BB80h when read.
6.1.23 MX3A S/PDIF Out Channel Status/Control
Default: 2000h
Two Channel AC’97 2.3 Audio Codec
16
Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E-MAIL: info@cornelius-consult.de
Rev1.01
http://www.cornelius-consult.de
Share Link: 