AL700 Просмотр технического описания (PDF) - AverLogic Technologies Inc
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AL700 Datasheet PDF : 82 Pages
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AL700/701/710
#1Ch), VSYNCWIDTH (#62h), and DISPVSTART (#1Dh) registers. Figure 2 shows the
output active window timing and the related registers.
For AL701, EncoderSel (#18h <0>) should be set to “1” in the initialization stage of AL701
because it does not support internal encoder mode.
7.3 Host Interface
AL700/701/710 supports I2C serial and proprietary parallel programming interfaces that can
be selected through SP_SEL pin. I2C serial interface requires two wires to access while the
proprietary parallel interface needs 11 wires. The communication speed of proprietary
parallel interface is much faster than I2C serial interface.
7.3.1 I2C Serial Interface
The I2C serial interface consists of SCL (serial clock) and SDA (serial data) signals.
There are internal pull-up circuits in AL700/701/710 for both SCL (equivalent to
H_WRB) and SDA (equivalent to H_BUS7) pins. When SP_SEL is pulled low, the I2C
serial interface is disabled and both SCL and SDA pins are pulled high. For both read and
write cycles, each byte is transferred from MSB bit to LSB bit. The Master/Slave device
samples and holds the SDA data at the rising edge of the SCL signal.
The read/write command format is as follows:
Write: <S> <Write SA> <A> <Register Index> <A> <Data> <A> <P>
Read:
<S> <Write SA> <A> <Register Index> <A> <S> <Read SA> <A> <Data>
<NA> <P>
Following are the details:
<S>: Start signal
SCL
High
SDA
High to Low
The Start signal appears at High to Low transition on the SDA line when SCL is High.
<Write SA>: Write Slave Address
The Write Slave Address is 70h or 72h.
<Read SA>: Read Slave Address
The Read Slave Address is 71h or 73h.
<Register Index>: Value of the AL700/710 register index.
<A>: Acknowledge stage
The host (master) generates acknowledge-related clock pulse. During the acknowledge
clock pulse, the host must release the SDA line (to High) in order that AL700/701/710
(slave) can pull down the SDA.
©2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 15
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