ALC202 Просмотр технического описания (PDF) - Unspecified
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ALC202 Datasheet PDF : 29 Pages
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Avance Logic, Inc.
ALC202
5. Design Suggestion
5.1 Clocking
The clock source of different configuration is listed below:
CODEC ID[1..0] BIT-CLK
Clock source
(12.288MHz)
00
Output 24.576M/14.318M crystal or external clock
source input from XTAL-IN*
01
Input 12.288MHz clock input from BIT-CLK
10
Input 12.288MHz clock input from BIT-CLK
11
Input 12.288MHz clock input from BIT-CLK
*The default clock source should be decided by XTLSEL, once 14.318MHz clock is selected,
internal digital PLL transfers it into 24.576MHz clock.
5.2 AC-Link
When ALC202 take serial data from AC97 controller, it sample SDATA_OUT on the falling
edge of BIT_CLK .When ALC202 send serial data to AC97 controller, it start to drive SDATA_IN on
the rising edge of BIT_CLK.
ALC202 will return any uninstalled bits or registers with 0 for read operation.. ALC202 also
stuff the unimplemented slot or bit with 0 in SDATA-IN. Note that AC-LINK is MSB-justified.
Refer to “Audio CODEC ’97 Component Specification Revision 2.1/2.2” for detail.
Slot#
SYNC
SDATA-OUT
012345
TAG CMD DATA PCM PCMR
L
6 7 8 9 10 11 12
SPDIF SPDIF
L
R
SDATA-IN
TAG ADDR DATA PCM PCMR
L
Fig5.2-1 Default ALC202 slot arrangement – CODEC ID = 00
Slot#
0 1 2 3 4 5 6 7 8 9 10 11 12
SYNC
SDATA-OUT TAG CMD DATA
SPDIF PCM PCMR SPDIF
L
L
R
SDATA-IN
TAG ADDR DATA PCM PCMR
L
Fig5.2-2 Default ALC202 slot arrangement – CODEC ID = 01, 10
Slot#
SYNC
SDATA-OUT
SDATA-IN
01234567
TAG CMD DATA
TAG ADDR DATA PCM PCMR
L
PCM
L
8 9 10 11 12
PCMR SPDIF SPDIF
L
R
- 18 -
Rev0.62
http://www.realtek.com.tw
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