ALC202 Просмотр технического описания (PDF) - Unspecified

Номер в каталоге

Компоненты Описание

производитель

ALC202

AC97 Audio CODEC

Unspecified 

Avance Logic, Inc.

ALC202

15:10

Reserved

9

R/W GPIO1 Output Control

0: Drive GPIO1 low.

1: Drive GPIO1 high.

8

R/W GPIO0 Output Control

0: Drive GPIO0 as low.

1: Drive GPIO0 as high.

7

NA Reserved

6

R/W JD Interrupt Status (JD_IS)¶

0: Not JD interrupt.

1: JD interrupt.

JD_IS= (MX78.2==1)&(MX76.6==1) & (JD low-to-high transition).

Write 1 to clear this status bit.

5

R/W GPIO1 Interrupt Status (GPIO1_IS). (When GPIO1 is used as input)¶

0: No GPIO1 interrupt.

1: GPIO1 interrupt.

GPIO1_IS= (MX76.1==0)&(MX76.5==1) & (GPIO1 low-to-high transition).

Write 1 to clear this status bit.

4

R/W GPIO0 Interrupt Status (GPIO0_IS). (When GPIO0 is used as input)¶

0: No GPIO0 interrupt.

1: GPIO0 interrupt.

GPIO0_IS= (MX76.0==0)&(MX76.4==1) & (GPIO0 low-to-high transition)

Write 1 to clear this status bit.

3

NA Reserved

2

R Jack-Detect Event (JDEVT)

0: No Jack-Detect event occurs.

1: Jack-Detect event occurs.

JDEVT = MX7A.0 & MX7A.1

1

R GPIO1 Input Status ·

0: GPIO1 is driven low by external device (input).

1: GPIO1 is driven high by external device (input).

0

R GPIO0 Input Status ·

0: GPIO0 is driven low by external device (input).

1: GPIO0 is driven high by external device (input).

¶GPIO interrupt (GPINT) in bit0 of SDATA_IN’s slot-12 = (MX78.4 | MX78.5 | MX78.6).

·When GPIO1/0 is used as input pin, its status will be also reflected in bit2/1 of SDIN’s slot-12. Once

GPIO1/0 is used as output pin, the bit2/1 of SDATA_IN’s slot-12 is always 0.

The GPIOx is internally pulled high by a weak resistor.

MX7A

Bit

15

14

13:8

7

6

5

Type

R

R/W

NA

R/W

R/W

R/W

Default: 57C0H

Function

Clock Source Selection (XTLSEL)

0: 24.576MHz crystal is used. DPLL is bypass. (XTLSEL is floating or open)

1: 14.318MHz crystal is used. 14.318Mà24.576M digital PLL is enabled.

(XTLSEL is pull low)

ENHPF, Digital high-pass filter to eliminate variation in DC offset.

0: Disable 1: Enable (default)

Reserved

Pin-48 Function Selection

0: S/PDIF output (default) 1: TEST

Output value of TEST (when bit-7 is set)

0: ADC CLK 1: DAC CLK

Pin-47 Function Selection

0: EAPD output (default) 1: Jack-Detect input

- 16 -

Rev0.62

http://www.realtek.com.tw

Preliminary

Share Link: