M28256 Просмотр технического описания (PDF) - STMicroelectronics
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M28256 Datasheet PDF : 20 Pages
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M28256
Table 3. Operating Modes 1
Mode
E
G
W
Read
VIL
VIL
VIH
Write
VIL
VIH
VIL
Stand-by / Write-Inhibit
VIH
X
X
Write Inhibit
X
X
VIH
X
VIL
X
Output Disable
Note: 1. X = VIH or VIL
X
VIH
X
DQ0-DQ7
Data Out
Data In
Hi-Z
Data Out or Hi-Z
Data Out or Hi-Z
Hi-Z
When Chip Enable is high, power consumption is
reduced.
Output Enable (G). The Output Enable input con-
trols the data output buffers, and is used to initiate
read operations.
Write Enable (W). The Write Enable input controls
whether the addressed location is to be read, from
or written to.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal VCC comparator in-
hibits the Write operations if the VCC voltage is
lower than VWI (see Table 4A and Table 4B). Once
the voltage applied on the VCC pin goes over the
VWI threshold (VCC>VWI), write access to the
memory is allowed after a time-out tPUW, as spec-
ified in Table 4A and Table 4B.
Further protection against data corruption is of-
fered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.
Read
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
Write
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as
shown in Figure 10 and Figure 11). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first). Af-
ter a delay, tWLQ5H, that cannot be shorter than the
value specified in Table 9A and Table 9B, the in-
ternal write cycle starts. It continues, under inter-
Table 4A. Power-Up Timing1 for M28256 (5V range)
(TA = 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V)
Symbol
Parameter
tPUR
Time Delay to Read Operation
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
VWI
Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
Table 4B. Power-Up Timing1 for M28256-W (3V range)
(TA = 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Parameter
tPUR
Time Delay to Read Operation
tPUW
Time Delay to Write Operation (once VCC ≥ VWI)
VWI
Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
Min.
Max.
Unit
1
µs
5
ms
3.0
4.2
V
Min.
Max.
Unit
1
µs
10
ms
1.5
2.5
V
4/20
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