M95256-BN5T Просмотр технического описания (PDF) - STMicroelectronics
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M95256-BN5T Datasheet PDF : 20 Pages
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M95256, M95128
Figure 9. Read EEPROM Array Operation Sequence
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
C
INSTRUCTION
16 BIT ADDRESS
D
15 14 13 3 2 1 0
HIGH IMPEDANCE
Q
DATA OUT
76543210
MSB
AI01793
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
Table 7. Address Range Bits
Device
M95256
M95128
Address Bits
A14-A0
A13-A0
Note: 1. b15 is Don’t Care on the M95256 series.
b15 and b14 are Don’t Care on the M95128 series.
SRWD bits, thereby putting the device in the hard-
ware protected mode.
An alternative method is to write the protected da-
ta, and to set the BP1, BP0 and SRWD bits, before
soldering the memory device to the board. Again,
this results in the memory device being placed in
its hardware protected mode.
If the W pin has been connected to VSS by a pull-
down resistor, the memory device can be taken
out of the hardware protected mode by driving the
W pin high, to override the pull-down resistor.
If the W pin has been directly soldered to VSS,
there is only one way of taking the memory device
out of the hardware protected mode: the memory
device must be de-soldered from the board, and
connected to external equipment in which the W
pin is allowed to be taken high.
Read Operation
The chip is first selected by holding S low. The se-
rial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in
during the rising edge of the clock (C).
The data stored in the memory, at the selected ad-
dress, is shifted out on the Q output pin. Each bit
is shifted out during the falling edge of the clock
(C) as shown in Figure 9. The internal address
counter is automatically incremented to the next
higher address after each byte of data has been
shifted out. The data stored in the memory, at the
next address, can be read by successive clock
pulses. When the highest address is reached, the
Figure 10. Write Enable Latch Sequence
S
01234567
C
D
HIGH IMPEDANCE
Q
AI02281
8/20
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