AK2500 Просмотр технического описания (PDF) - Asahi Kasei Microdevices

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AK2500

DS3/STS-l Analog Line Receiver

Asahi Kasei Microdevices 

ASAHI KASEI

[AK2500]

Clock Recovery

The receiver uses a Master/Slave Phase Lock Loop (PLL) to recover clock. The Master PLL has its center

frequency set using the reference clock, EXCLK. The same control voltage that is generated to center the

frequency of the Master VCO isalsoused tocenter the frequency of the Slave VCO. This insures continuous

frequen~lock of the Slave PLL, andalso insures immuni~to false lock. The Slave VCOisphase locked to

the received data stream.

If a valid input signal is assumed to be already present at the analog input, the maximum time between the

application of device power and error-free operation is typically 20 ms. If power has already been applied and

input data is then lost, the interval between the restoration of valid data and error-free operation is nominally

1.0 ms and typically no longer than 4 ms.

An external loop filter is used by the slave PLL, allowing the jitter tolerance and transfer function to be tailored

for a variety of applications. The component values for the capacitor is 0.1 u F* 20Y0. A low-leakage (e.g.,

ceramic) capacitor should be used.

TMC 1 TMC2

Mode

o

0 Normal Coax Operation

Coax-compatible analog signal input on IUN (pin 4)

o

1 *Loopback Coax Operation

1

1 TMC 1 used to select between two coax- compatible

analog signal; TMC 1=1OWselects pin 4 for normal

operation: TMC l=high selects pin 3 for loopback.

1

0 Optical Operation

Output of optical receiver input on MN (pin 4)

Table 1. Mode Control

*Note

Loopback Mode is not available in the current revision. TMC2 bit must be set O.

Pin 4

Pin 3

Definition Definition

Input

RLOL

output

Input

LIN

Input

Input

RLOL

output

Loss-of-Lock Detection

The PLL monitors the retimed data to detect possible phase-lock which is 180° out of a normal phase

alignment. Loss of lock is detected if either or both of the following conditions exist:

the frequenq difference between the Slave PLL clock and the incoming signal (on FLIN/AIN)exceeds than

approximately * O.s~o.

In the normal coax operation, seven consecutive O’sare detected in the retimed data (indicates possible lock

which is 180° out of normal alignment). In the optical operation, any consecutive O’sare not detected.

External Reference Clock

An external reference clock is used to set the frequency of the Master PLL. The reference clock should be

within & 100ppm of the line signal.

0133-E-00

-1o-

1996/7

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