MAX542 Просмотр технического описания (PDF) - Advanced Micro Devices

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MAX542

256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms

Advanced Micro Devices 

PIN DESCRIPTION

A0–A14

Address Inputs for memory locations. Internal latches

hold addresses during write cycles.

CE# (E#)

Chip Enable active low input activates the chip’s control

logic and input buffers. Chip Enable high will deselect

the device and operates the chip in stand-by mode.

DQ0-DQ7

Data Inputs during memory write cycles. Internal

latches hold data during write cycles. Data Outputs

during memory read cycles.

NC

No Connect-corresponding pin is not connected

internally to the die.

OE# (G#)

Output Enable active low input gates the outputs of the

device through the data buffers during memory read

cycles. Output Enable is high during command

sequencing and program/erase operations.

VCC

Power supply for device operation. (5.0 V ± 5% or 10%)

VPP

Program voltage input. VPP must be at high voltage in

order to write to the command register. The command

register controls all functions required to alter the mem-

ory array contents. Memory contents cannot be altered

when VPP ≤ VCC +2 V.

VSS

Ground.

WE# (W)

Write Enable active low input controls the write function

of the command register to the memory array. The target

address is latched on the falling edge of the Write En-

able pulse and the appropriate data is latched on the ris-

ing edge of the pulse. Write Enable high inhibits writing

to the device.

Am28F256A

7

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