M48Z35-70PC1TR Просмотр технического описания (PDF) - STMicroelectronics
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M48Z35-70PC1TR Datasheet PDF : 18 Pages
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Table 3. Operating Modes (1)
Mode
VCC
E
G
Deselect
VIH
X
Write
Read
4.75V to 5.5V
or
4.5V to 5.5V
VIL
X
VIL
VIL
Read
VIL
VIH
Deselect
VSO to VPFD (min) (2)
X
X
Deselect
≤ VSO
X
X
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Figure 3. Block Diagram
M48Z35, M48Z35Y
W
DQ0-DQ7
Power
X
High Z
Standby
VIL
DIN
VIH
DOUT
VIH
High Z
Active
Active
Active
X
High Z
CMOS Standby
X
High Z Battery Back-up Mode
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
POWER
VPFD
32K x 8
SRAM ARRAY
A0-A14
DQ0-DQ7
E
W
G
VCC
VSS
AI01619B
The M48Z35/35Y is a non-volatile pin and function
equivalent to any JEDEC standard 32K x8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed. The 28 pin 600mil DIP
CAPHAT™ houses the M48Z35/35Y silicon with a
long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPHAT housing
is keyed to prevent reverse insertion.
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