ADV7340/ADV7341
TIMING DIAGRAMS
The following abbreviations are used in Figure 2 to Figure 13:
• t9 = Clock high time
• t10 = Clock low time
• t11 = Data setup time
• t12 = Data hold time
CLKIN_A
t9 t10
t12
CONTROL S_HSYNC,
INPUTS S_VSYNC
• t13 = Control output access time
• t14 = Control output hold time
In addition, refer to Table 31 for the ADV7340/ADV7341 input
configuration.
IN SLAVE MODE
S9 TO S0/
Y9 TO Y0*
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
t11
t13
CONTROL
OUTPUTS
t14
IN MASTER/SLAVE MODE
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 2. SD Only, 8-/10-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
CLKIN_A
CONTROL S_HSYNC,
INPUTS S_VSYNC
S9 TO S0/
Y9 TO Y0*
t9 t10
Y0
t12
Y1
IN SLAVE MODE
Y2
Y3
Y9 TO Y0/
C9 TO C0*
Cb0
Cr0
Cb2
Cr2
t11
t13
CONTROL
OUTPUTS
t14
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 3. SD Only, 16-/20-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
IN MASTER/SLAVE MODE
Rev. 0 | Page 10 of 88