ADV7183AKST(RevA) Просмотр технического описания (PDF) - Analog Devices

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производитель

ADV7183AKST
(Rev.:RevA)

Multiformat SDTV Video Decoder

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADV7183A

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

VS 1

HS 2

DGND 3

DVDDIO 4

P11 5

P10 6

P9 7

P8 8

DGND 9

DVDD 10

NC 11

SFL 12

NC 13

DGND 14

DVDDIO 15

NC 16

NC 17

NC 18

P7 19

P6 20

ADV7183A

TOP VIEW

(Not to Scale)

60 AIN5

59 AIN11

58 AIN4

57 AIN10

56 AGND

55 CAP C2

54 CAP C1

53 AGND

52 CML

51 REFOUT

50 AVDD

49 CAP Y2

48 CAP Y1

47 AGND

46 AIN3

45 AIN9

44 AIN2

43 AIN8

42 AIN1

41 AIN7

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

NC = NO CONNECT

Figure 5. 80-Lead LQFP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

3, 9, 14, 31, 71

DGND

39, 40, 47, 53, 56 AGND

4, 15

DVDDIO

10, 30, 72

DVDD

50

AVDD

38

PVDD

41–46, 57–62

AIN1–AIN12

11, 13, 16–18, 25, NC

34, 35, 63, 65, 69,

70, 77, 78

5–8, 19–24,

32, 33, 73–76

P0–P15

2

HS

1

VS

80

FIELD

67

SDA

68

SCLK

66

ALSB

64

RESET

27

LLC1

26

LLC2

Type

G

G

P

P

P

P

I

O

O

O

O

I/O

I

I

I

O

O

Function

Digital Ground.

Analog Ground.

Digital I/O Supply Voltage (3.3 V).

Digital Core Supply Voltage (1.8 V).

Analog Supply Voltage (3.3 V).

PLL Supply Voltage (1.8 V).

Analog Video Input Channels.

No Connect Pins.

Video Pixel Output Port.

HS is a horizontal synchronization output signal.

VS is a vertical synchronization output signal.

FIELD is a field synchronization output signal.

I2C Port Serial Data Input/Output Pin.

I2C Port Serial Clock Input (Max Clock Rate of 400 kHz).

This pin selects the I2C address for the ADV7183A. ALSB set to Logic 0 sets the address for a

write as 0x40; for ALSB set to logic high, the address selected is 0x42.

System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to

reset the ADV7183A circuitry.

This is a line-locked output clock for the pixel data output by the ADV7183A. Nominally

27 MHz, but varies up or down according to video line length.

This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the

ADV7183A. Nominally 13.5 MHz, but varies up or down according to video line length.

Rev. A | Page 11 of 104

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