ADV7177 Просмотр технического описания (PDF) - Analog Devices
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ADV7177 Datasheet PDF : 38 Pages
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ADV7177/ADV7178
Pin
No.
1, 20, 28, 30
2
3–10, 12–14,
37–41
11
15
16
Mnemonic
VAA
CLOCK/2
P15–P0
OSD_EN
HSYNC
FIELD/VSYNC
17
18
19, 21, 29, 42
22
BLANK
ALSB
GND
RESET
23
24
25
26
27
31
32
33
34–36
43
44
SCLOCK
SDATA
COMP
DAC C
DAC B
DAC A
VREF
RSET
OSD_0–2
CLOCK
CLOCK
PIN FUNCTION DESCRIPTIONS
Input/
Output Function
P
+5 V Supply.
O
Synchronous Clock output signal. Can be either 27 MHz or 13.5 MHz; this
can be controlled by MR32 and MR33 in Mode Register 3.
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb
Pixel Port (P15–P0). P0 represents the LSB.
I
Enables OSD input data on the video outputs.
I/O
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to
output (Master Mode) or accept (Slave Mode) Sync signals.
I/O
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This
pin may be configured to output (Master Mode) or accept (Slave Mode)
these control signals.
I/O
Video Blanking Control Signal. The pixel inputs are ignored when this is
Logic Level “0.” This signal is optional.
I
TTL Address Input. This signal sets up the LSB of the MPU address.
G
Ground Pin.
I
The input resets the on-chip timing generator and sets the ADV7177/ADV7178
into default mode. This is NTSC operation, Timing Slave Mode 0, 8-Bit
Operation, 2 × Composite and S VHS out.
I
MPU Port Serial Interface Clock Input.
I/O
MPU Port Serial Data Input/Output.
O
Compensation Pin. Connect a 0.1 µF Capacitor from COMP to VAA.
O
DAC C Analog Output.
O
DAC B Analog Output.
O
DAC A Analog Output.
I/O
Voltage Reference Input for DACs or Voltage Reference Output (1.2 V).
I
A 300 Ω resistor connected from this pin to GND is used to control full-scale
amplitudes of the Video Signals.
I
On Screen Display Inputs.
O
Crystal Oscillator output (to crystal). Leave unconnected if no crystal is used.
I
Crystal Oscillator input. If no crystal is used this pin can be driven by an
external TTL Clock source; it requires a stable 27 MHz reference Clock for
standard operation. Alternatively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL)
can be used for square pixel operation.
–10–
REV. 0
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