ADV7150LS170 Просмотр технического описания (PDF) - Analog Devices

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ADV7150LS170

CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC

Analog Devices 

ADV7150

ADDRESS

REGISTER

ADDR

(A7–A0)

MODE

REGISTER

(MR1)

CONTROL REGISTERS

PIXEL MASK

REGISTER

TEST

REGISTERS

COMMAND

REGISTERS

(CR1–CR3)

ID

REGISTER

REVISION

REGISTER

DATA TO

PALETTES

30

COLOR REGISTERS

RED

GREEN

BLUE

REGISTER REGISTER REGISTER

MPU PORT

CE R/W C0 C1

10 (8+2)

D9 – D0

Figure 27. MPU Port and Register Configuration

Data is read from the color palette by first writing to the address

register of the color palette location to be read. The MPU per-

forms three successive read cycles from each of the red, green

and blue locations (10-bit or 8-bit) of the RAM. An internal

pointer moves from red to green to blue after each read is com-

pleted. This pointer is reset to red after a blue read or whenever

the address register is written. The address register then auto-

matically increments to point to the next RAM location, and a

similar red, green and blue palette read sequence is performed.

The address register resets to 00H following a blue read cycle of

color palette RAM location FFH.

Register Accesses

The MPU can write to or read from all of the ADV7150s regis-

ters. C0 and C1 determine whether the Mode Register or Ad-

dress Register is being accessed. Access to these registers is

direct. The Control Registers are accessed indirectly. The

Address Register must point to the desired Control Register.

Figure 28 along with the 8-bit and 10-bit Interface Truth Tables

illustrate the structure and protocol for device communication

over the MPU port.

MODE REGISTER

(MR17–MR10)

C1 = 1

C0 = 1

C1 = 1

C0 = 0

ADDRESS

REGISTER

(A15–A0)

CONTROL

REGISTERS

00H

PIXEL TEST REGISTER

R

G

B

01H

DAC TEST REGISTER

R

G

B

02H

SYNC, BLANK & IPLL

TEST REGISTER

03H

ID REGISTER (READ ONLY)

04H

PIXEL MASK REGISTER

05H

COMMAND REGISTER 1

06H

COMMAND REGISTER 2

07H

COMMAND REGISTER 3

08H

RESERVED* (READ ONLY)

09H

RESERVED* (READ ONLY)

0AH

RESERVED* (READ ONLY)

0BH

REVISION REGISTER

ADDRESS REGISTER C1 = 0

(A7–A0)

C0 = 0

C1 = 0

C0 = 1

RED

REGISTER

(R9–R0)

GREEN

REGISTER

(G9–G0)

BLUE

REGISTER

(B9–B0)

POINTS TO LOCATION

CORRESPONDING TO

ADDRESS REG (A7–A0)

LOOK-UP TABLE RAM

(256 x 30)

ADDRESS REG = ADDRESS REG + 1

* THIS REGISTER IS READ ONLY.

A READ CYCLE WILL RETURN ZEROS "00".

Figure 28. Internal Register Configuration and Address Decoding

–18–

REV. A

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