ADT7467ARQZ-R71 Просмотр технического описания (PDF) - ON Semiconductor
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ADT7467ARQZ-R71 Datasheet PDF : 77 Pages
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ADT7467
Parameter
Min
OPEN-DRAIN DIGITAL OUTPUTS, PWM1 to PWM3,
XTO
Current Sink, IOL
Output Low Voltage, VOL
High Level Output Current, IOH
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Current, IOH
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
−0.3
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
Input High Current, IIH
−1
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING
Clock Frequency, fSCLK
10
Glitch Immunity, tSW
Bus Free Time, tBUF
4.7
Start Setup Time, tSU; STA
4.7
Start Hold Time, tHD; STA
4.0
SCL Low Time, tLOW
4.7
SCL High Time, tHIGH
4.0
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU; DAT
250
Data Hold Time, tHD; DAT
300
Detect Clock Low Timeout, tTIMEOUT
15
Typ
Max Unit Test Conditions/Comments
8.0
mA
0.4
V
IOUT = −8.0 mA, VCC = 3.3 V
0.1
1.0
μA
VOUT = VCC
0.4
V
IOUT = −4.0 mA, VCC = 3.3 V
0.1
1.0
μA
VOUT = VCC
V
0.4
V
500
mV
V
5.5
V
Maximum input voltage
0.8
V
V
Minimum input voltage
0.5
V p-p
0.75 × VCCP
V
0.4
V
μA
VIN = VCC
1
μA
VIN = 0
5
pF
See Figure 2
400
kHz
50
ns
μs
μs
μs
μs
50
μs
1000 ns
300
μs
ns
ns
35
ms Can be optionally disabled
SCL
tLOW tR
tHD; STA
tHD; DAT
tF
tHIGH
tSU; DAT
tHD; STA
tSU; STA
tSU; STO
SDA
tBUF
P
S
S
P
Figure 2. Serial Bus Timing Diagram
Rev. 3 | Page 4 of 77 | www.onsemi.com
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