GS818QV36D-250I Просмотр технического описания (PDF) - Giga Semiconductor
Номер в каталоге
Компоненты Описание
производитель
GS818QV36D-250I Datasheet PDF : 29 Pages
| |||
Preliminary
GS818QV18/36D-200/167/133
Pin Description Table
Symbol
SA
NC
R
W
BW0–BW1
Description
Synchronous Address Inputs
No Connect
Synchronous Read
Synchronous Write
Synchronous Byte Writes
BW0–BW3
Synchronous Byte Writes
K
Input Clock
K
Input Clock
C
Output Clock
C
Output Clock
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock Input
TDO
Test Data Output
VREF
HSTL Input Reference Voltage
ZQ
Output Impedance Matching Input
MCL
Must Connect Low
CQ
Synchronous Echo Clock Output
CQ
Synchronous Echo Clock-bar Output
Q0–Q35
Synchronous Data Outputs
D0–D17
Synchronous Data Inputs
Q0–Q17
Synchronous Data Outputs
VDD
Power Supply
VDDQ
Isolated Output Buffer Supply
VSS
Power Supply: Ground
Note: NC = Not Connected to die or any other pin
Type
Input
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
—
Output
Output
Output
Input
Output
Supply
Supply
Supply
Comments
—
—
Active Low
Active Low
Active Low
x18 Version
Active Low
x36 Version
Active High
Active Low
Active High
Active Low
—
—
—
—
—
—
—
Echoes C or K Clock
Echoes C or K Clock
x36 Version
x18 Version
x18 Version
2.5 V Nominal
1.5 V Nominal
—
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed.
Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in
applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the
RAM’s bandwidth in half.
Rev: 1.01 11/2002
4/29
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Share Link: 