ADSP-BF537 Просмотр технического описания (PDF) - Analog Devices

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ADSP-BF537

Blackfin® Embedded Processor

Analog Devices 

CLKOUT

CLKBUF

BLACKFIN

TO PLL CIRCUITRY

EN

EN

CLKIN

330⍀*

XTAL

FOR OVERTONE

OPERATION ONLY:

18pF*

18pF*

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED

DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE

ANALYZE CAREFULLY.

Figure 6. External Crystal Connections

Because of the default 10x PLL multiplier, providing a 50 MHz

CLKIN exceeds the recommended operating conditions of the

lower speed grades. Because of this restriction, a 50 MHz RMII

PHY cannot be clocked directly from the CLKBUF pin. Either

provide a separate 50 MHz clock source, or use an RMII PHY

with 25 MHz clock input options. The CLKBUF output is active

by default and can be disabled using the VR_CTL register for

power savings.

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 7, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a programmable 0.5× to 64× multiplication

factor (bounded by specified minimum and maximum VCO

frequencies). The default multiplier is 10×, but it can be modi-

fied by a software instruction sequence in the PLL_CTL register.

On-the-fly CCLK and SCLK frequency changes can be effected

by simply writing to the PLL_DIV register. Whereas the maxi-

mum allowed CCLK and SCLK rates depend on the applied

voltages VDDINT and VDDEXT, the VCO is always permitted to run

up to the frequency specified by the part’s speed grade. The

CLKOUT pin reflects the SCLK frequency to the off-chip world.

It belongs to the SDRAM interface, but it functions as reference

signal in other timing specifications as well. While active by

default, it can be disabled using the EBIU_SDGCTL and

EBIU_AMGCTL registers.

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

ADSP-BF534/ADSP-BF536/ADSP-BF537

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COURSE” ADJUSTMENT

ON THE FLY

CLKI N

PLL

0.5ϫ - 64ϫ

، 1, 2, 4, 8

VCO

، 1 TO 15

CCLK

SCLK

SCLK ≤ CCLK

SCLK ≤ 133MHz

Figure 7. Frequency Modification Methods

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of fSCLK. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

Table 6. Example System Clock Ratios

Signal Name

SSEL3–0

0001

0110

1010

Example Frequency Ratios

Divider Ratio (MHz)

VCO/SCLK VCO

SCLK

1:1

100

100

6:1

300

50

10:1

500

50

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

Table 7. Core Clock Ratios

Signal Name

CSEL1–0

00

01

10

11

Example Frequency Ratios

Divider Ratio (MHz)

VCO/CCLK VCO

CCLK

1:1

300

300

2:1

300

150

4:1

500

125

8:1

200

25

The maximum CCLK frequency not only depends on the part’s

speed grade (see Ordering Guide on Page 66), it also depends on

the applied VDDINT voltage. See Table 12 and Table 13 for details.

The maximal system clock rate (SCLK) depends on the chip

package and the applied VDDEXT voltage (see Table 16).

Rev. B | Page 15 of 68 | July 2006

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