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ADSP-BF537

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF534/ADSP-BF536/ADSP-BF537

Table 5. Power Domains

Power Domain

All internal logic, except RTC

RTC internal logic and crystal I/O

All other I/O

VDD Range

VDDINT

VDDRTC

VDDEXT

The dynamic power management feature allows both the pro-

cessor’s input voltage (VDDINT) and clock frequency (fCCLK) to be

dynamically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in power dissipation, while reducing the voltage by

25% reduces power dissipation by more than 40%. Further,

these power savings are additive, in that if the clock frequency

and supply voltage are both reduced, the power savings can be

dramatic, as shown in the following equations.

The power savings factor is calculated as:

power savings factor

=

-f--C---C---L--K---R--E---D--

fCCLKNOM

×

⎛

⎝

V-V----D-D--D-D--I-IN-N--T-T--N-R--OE---DM--⎠⎞

2

×

⎛

⎝

-T----R---E--D--

TNOM

⎞

⎠

where the variables in the equations are:

fCCLKNOM is the nominal core clock frequency

fCCLKRED is the reduced core clock frequency

VDDINTNOM is the nominal internal supply voltage

VDDINTRED is the reduced internal supply voltage

TNOM is the duration running at fCCLKNOM

TRED is the duration running at fCCLKRED

The percent power savings is calculated as:

% power savings = (1 – power savings factor) × 100%

VOLTAGE REGULATION

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor pro-

vides an on-chip voltage regulator that can generate processor

core voltage levels (0.85 V to 1.2 V guaranteed from –5% to

+10%) from an external 2.25 V to 3.6 V supply. Figure 5 shows

the typical external components required to complete the power

management system. The regulator controls the internal logic

voltage levels and is programmable with the voltage regulator

control register (VR_CTL) in increments of 50 mV. To reduce

standby power consumption, the internal voltage regulator can

be programmed to remove power to the processor core while

keeping I/O power supplied. While in hibernate mode, VDDEXT

can still be applied, eliminating the need for external buffers.

The voltage regulator can be activated from this power-down

state by asserting the RESET pin, which then initiates a boot

sequence. The regulator can also be disabled and bypassed at the

user’s discretion.

VDDEXT

VDDINT

100µF

100µF 1µF

10µH

0.1µF

ZHCS1000

2.25V TO 3.6V

INPUT VOLTAGE

RANGE

NDS8434

VROUT1-0

EXTERNAL COMPONENTS

NOTE: VROUT1-0 SHOULD BE TIED TOGETHER EXTERNALLY

AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO NDS8434.

Figure 5. Voltage Regulator Circuit

CLOCK SIGNALS

The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor can be

clocked by an external crystal, a sine wave input, or a buffered,

shaped clock derived from an external clock oscillator.

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

Alternatively, because the processors include an on-chip oscilla-

tor circuit, an external crystal may be used. For fundamental

frequency operation, use the circuit shown in Figure 6. A

parallel-resonant, fundamental frequency, microprocessor-

grade crystal is connected across the CLKIN and XTAL pins.

The on-chip resistance between CLKIN and the XTAL pin is in

the 500 kΩ range. Further parallel resistors are typically not rec-

ommended. The two capacitors and the series resistor shown in

Figure 6 fine-tune phase and amplitude of the sine frequency.

The capacitor and resistor values shown in Figure 6 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations of multiple

devices over temperature range.

A third-overtone crystal can be used for frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 6. A design procedure for third-overtone oper-

ation is discussed in detail in application note EE-168.

The CLKBUF pin is an output pin, and is a buffer version of the

input clock. This pin is particularly useful in Ethernet applica-

tions to limit the number of required clock sources in the

system. In this type of application, a single 25 MHz or 50 MHz

crystal may be applied directly to the processors. The 25 MHz or

50 MHz output of CLKBUF can then be connected to an exter-

nal Ethernet MII or RMII PHY device.

Rev. B | Page 14 of 68 | July 2006

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