ADSP-BF516KSWZ-4(RevD) Просмотр технического описания (PDF) - Analog Devices
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ADSP-BF516KSWZ-4 Datasheet PDF : 68 Pages
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ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
ADDRESS ARITHMETIC UNIT
DA1 32
DA0 32
I3 L3 B3
M3
I2 L2 B2
M2
I1 L1 B1
M1
I0 L0 B0
M0
32
RAB
DAG1
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
PREG
SD
32
LD1
32
LD0
32
32
32
R7.H R7.L
R6.H R6.L
R5.H R5.L
R4.H R4.L
16
R3.H R3.L
8
8
8
R2.H R2.L
R1.H R1.L
BARREL
R0.H R0.L
SHIFTER
40
A0
40 40
32
32
DATA ARITHMETIC UNIT
ASTAT
16
8
40
A1
SEQUENCER
ALIGN
DECODE
LOOP BUFFER
CONTROL
UNIT
Figure 2. Blackfin Processor Core
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit
Rev. D | Page 4 of 68 | April 2014
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