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ADSP-21MOD870

Internet Gateway Processor

Analog Devices 

ADSP-21mod870

ratio. The default form of the instruction, when no clock divisor

is given, is the standard IDLE instruction.

When the IDLE (n) instruction is used, it effectively slows down

the processor’s internal clock and thus its response time to in-

coming interrupts. The one-cycle response time of the standard

idle state is increased by n, the clock divisor. When an enabled

interrupt is received, the ADSP-21mod870 will remain in the idle

state for up to a maximum of n processor cycles (n = 16, 32, 64,

or 128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

faster rate than can be serviced, due to the additional time the

processor takes to come out of the idle state (a maximum of n

processor cycles).

SYSTEM INTERFACE

Figure 3 shows a typical multichannel modem configuration

with the ADSP-21mod870. A line interface can be used to

connect the multichannel subscriber or client data stream to the

multichannel serial port of the ADSP-21mod870. The ADSP-

21mod870 can support 24 or 32 channels. The IDMA port of

the ADSP-21mod870 is used to give a host processor full access

to the internal memory of the ADSP-21mod870. This lets the

host dynamically configure the ADSP-21mod870 by loading code

and data into its internal memory. This configuration also lets

the host access server data directly from the ADSP-21mod870’s

internal memory. In this configuration, the ADSP-21mod870

should be put into host memory mode where Mode C = 1,

Mode B = 0 and Mode A = 1 (see Table II).

CLOCK SIGNALS

The ADSP-21mod870 can be clocked by either a crystal or a

TTL-compatible clock signal.

The CLKIN input cannot be halted, changed during operation,

or operated below the specified frequency during normal opera-

tion. The only exception is while the processor is in the power-

down state. For additional information, refer to Chapter 9,

ADSP-2100 Family User’s Manual, Third Edition, for detailed

information on this power-down feature.

If an external clock is used, it should be a TTL-compatible

signal running at half the instruction rate. The signal is con-

nected to the processor’s CLKIN input. When an external clock

is used, the XTAL input must be left unconnected.

The ADSP-21mod870 uses an input clock with a frequency

equal to half the instruction rate; a 26 MHz input clock yields a

19 ns processor cycle (which is equivalent to 52 MHz). Nor-

mally, instructions are executed in a single processor cycle. All

device timing is relative to the internal instruction clock rate,

which is indicated by the CLKOUT signal when enabled.

Because the ADSP-21mod870 includes an on-chip oscillator

circuit, an external crystal may be used. The crystal should be

connected across the CLKIN and XTAL pins, with two capaci-

tors connected as shown in Figure 4. Capacitor values are de-

pendent on crystal type and should be specified by the crystal

manufacturer. A parallel-resonant, fundamental frequency,

microprocessor-grade crystal should be used.

A clock output (CLKOUT) signal is generated by the processor

at the processor’s cycle rate. This is enabled and disabled by the

CLKODIS bit in the SPORT0 Autobuffer Control Register.

LINE

INTERFACE

CALL

CONTROL

T1, E1, PRI,

xDSL, ATM

SP0

ADSP-

21mod870

IDMA

SP0

ADSP-

21mod870

IDMA

SP0

ADSP-

21mod870

IDMA

HOST BUS

IDMA

ADSP-

21mod870

SP0

IDMA

ADSP-

21mod870

SP0

IDMA

ADSP-

21mod870

SP0

SP0

ADSP-

21mod870

IDMA

IDMA

ADSP-

21mod870

SP0

HOST

(2183)

LAN OR

INTERNET

ADSP-21mod870 FUNCTIONS

• V.34/56k MODEM

• V.17 FAX

• V.42, V.42bis, MNP2-5

DTMF DIALING

CALLER ID

HDLC PROTOCOL

HOST FUNCTIONS

• MULTI-DSP CONTROL AND OVERLAY

MANAGEMENT

• SERVICE 32 DSPs/HOST

• DATA PACKETIZING

Figure 3. Network Access System

REV. 0

CLKIN

XTAL

DSP

CLKOUT

Figure 4. External Crystal Connections

–7–

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