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ADSP-21MOD870

Internet Gateway Processor

Analog Devices 

ADSP-21mod870

synchronous serial interface with optional companding in hard-

ware and a wide variety of framed or frameless data transmit

and receive modes of operation.

Each port can generate an internal programmable serial clock or

accept an external serial clock.

The ADSP-21mod870 provides up to 13 general-purpose flag

pins. The data input and output pins on SPORT1 can be alter-

natively configured as an input flag and an output flag. In addi-

tion, there are eight flags that are programmable as inputs or

outputs, and three flags that are always outputs.

A programmable interval timer generates periodic interrupts. A

16-bit count register (TCOUNT) decrements every n processor

cycles, where n is a scaling value stored in an 8-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-21mod870 incorporates two complete synchronous

serial ports (SPORT0 and SPORT1) for serial communications

and multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-21mod870

SPORTs. For additional information on Serial Ports, refer to the

ADSP-2100 Family User’s Manual, Third Edition.

• SPORTs are bidirectional and have a separate, double-

buffered transmit and receive section.

• SPORTs can use an external serial clock or generate their

own serial clock internally.

• SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulsewidths and timings.

• SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of

data with one overhead cycle per data word. An interrupt is

generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive

and transmit a 24 or 32 word, time-division multiplexed,

serial bitstream.

• SPORT1 can be configured to have two external interrupts

(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The

internally generated serial clock may still be used in this

configuration.

PIN DESCRIPTIONS

The ADSP-21mod870 is available in a 100-lead LQFP package.

To maintain maximum functionality and reduce package size

and pin count, some serial port, programmable flag, interrupt,

and external bus pins have dual, multiplexed functionality. The

external bus pins are configured during RESET, while serial

port pins are software configurable during program execution.

Flag and interrupt functionality is retained concurrently on

multiplexed pins. The following table shows the common-mode

pins. When pin functionality is configurable, the default state is

shown in plain text, alternate functionality is in italics.

Common-Mode Pins

Pin

Name(s)

# Input/

of Out-

Pins put Function

RESET

BR

BG

BGH

DMS

PMS

IOMS

BMS

CMS

RD

WR

IRQ2/

PF7

IRQL1/

PF6

IRQL0/

PF5

IRQE/

PF4

1I

Processor Reset Input

1I

Bus Request Input

1 O Bus Grant Output

1 O Bus Grant Hung Output

1 O Data Memory Select Output

1 O Program Memory Select Output

1 O Memory Select Output

1 O Byte Memory Select Output

1 O Combined Memory Select Output

1 O Memory Read Enable Output

1 O Memory Write Enable Output

1I

Edge- or Level-Sensitive

Interrupt Request1

I/O Programmable I/O Pin

1I

Level-Sensitive Interrupt Requests1

I/O Programmable I/O Pin

1I

Level-Sensitive Interrupt Requests1

I/O Programmable I/O Pin

1I

Edge-Sensitive Interrupt Requests1

I/O Programmable I/O Pin

Mode D/

PF3

1I

Mode Select Input—Checked

only During RESET

I/O Programmable I/O Pin During

Normal Operation

Mode C/

PF2

1I

Mode Select Input—Checked

only During RESET

I/O Programmable I/O Pin During

Normal Operation

Mode B/

PF1

1I

Mode Select Input—Checked

only During RESET

I/O Programmable I/O Pin During

Normal Operation

Mode A/

PF0

1I

Mode Select Input—Checked

only During RESET

I/O Programmable I/O Pin During

Normal Operation

CLKIN, XTAL 2 I

Clock or Quartz Crystal Input

CLKOUT

1 O Processor Clock Output

SPORT0

5 I/O

SPORT12

5 I/O

or Interrupts and Flags:

IRQ0 (RFS1) 1 I

IRQ1 (TFS1) 1 I

FI (DR1)

1I

FO (DT1)

1O

PWD

1I

Serial Port 0 Pins (TFS0, RFS0,

DT0, DR0, SCLK0)

Serial Port 1 Pins (TFS1, RFS1,

DT1, DR1, SCLK1)

External Interrupt Request #0

External Interrupt Request #1

Flag Input Pin

Flag Output Pin

Power-Down Control Input

PWDACK

1 O Power-Down Control Output

FL0, FL1, FL2 3 O Output Flags

VDD and GND

EZ-Port

16 I

9 I/O

Power and Ground

For Emulation Use

NOTES

1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the

corresponding interrupts, the DSP will vector to the appropriate interrupt vector address

when the pin is asserted, either by external devices or set as a programmable flag.

2SPORT configuration determined by the DSP System Control Register. Software

configurable.

–4–

REV. 0

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