ADSP-21992 Просмотр технического описания (PDF) - Analog Devices
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ADSP-21992 Datasheet PDF : 60 Pages
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ADSP-21992
register to supply the most significant eight address bits.
Before a cross page jump or call, the program must set the
program sequencer IJPG register to the appropriate mem-
ory page.
The ADSP-21992 has 4K words of on-chip ROM that holds
boot routines. The DSP starts executing instructions from the
on-chip boot ROM, which starts the boot process. For more
information, see Booting Modes on Page 14. The on-chip boot
ROM is located on Page 255 in the DSP memory space map,
starting at address 0xFF0000.
External (Off-Chip) Memory
Each of the off-chip memory spaces of the ADSP-21992 has a
separate control register, so applications can configure unique
access parameters for each space. The access parameters include
read and write wait counts, wait state completion mode, I/O
clock divide ratio, write hold time extension, strobe polarity,
and data bus width. The core clock and peripheral clock ratios
influence the external memory access strobe widths. For more
information, see Clock Signals on Page 13. The off-chip mem-
ory spaces are:
• External memory space (MS3–0 pins)
• I/O memory space (IOMS pin)
• Boot memory space (BMS pin)
All of these off-chip memory spaces are accessible through the
external port, which can be configured for 8-bit or 16-bit
data widths.
External Memory Space
External memory space consists of four memory banks. These
banks can contain a configurable number of 64K word pages. At
reset, the page boundaries for external memory have Bank0
containing pages 1 to 63, Bank1 containing pages 64 to 127,
Bank2 containing pages 128 to 191, and Bank3 containing pages
192 to 254. The MS3-0 memory bank pins select Banks 3-0,
respectively. Both the ADSP-2199x core and DMA capable
peripherals can access the DSP external memory space.
All accesses to external memory are managed by the external
memory interface unit (EMI).
I/O Memory Space
The ADSP-21992 supports an additional external memory
called I/O memory space. The I/O space consists of 256 pages,
each containing 1024 addresses. This space is designed to sup-
port simple connections to peripherals (such as data converters
and external registers) or to bus interface ASIC data registers.
The first 32K addresses (I/O pages 0 to 31) are reserved for on-
chip peripherals. The upper 224K addresses (I/O pages 32 to
255) are available for external peripheral devices. External I/O
pages have their own select pin (IOMS). The DSP instruction set
provides instructions for accessing I/O space.
0x00::0x000
0x1F::0x3FF
0x20::0x000
ON-CHIP
PERIPHERALS
16-BITS
0xFF::0x3FF
OFF-CHIP
PERIPHERALS
16-BITS
PAGES 0 TO 31
1024 WORDS/PAGE
2 PERIPHERALS/PAGE
PAGES 32 TO 255
1024 WORDS/PAGE
Figure 4. I/O Memory Map
Boot Memory Space
Boot memory space consists of one off-chip bank with 254
pages. The BMS memory bank pin selects boot memory space.
Both the ADSP-2199x core and DMA capable peripherals can
access the DSP off-chip boot memory space. After reset, the
DSP always starts executing instructions from the on-chip
boot ROM.
0x01 0000
0xFE 0000
OFF-CHIP
BOOT MEMORY
16-BITS
PAGES 1 TO 254
64K WORDS/PAGE
Figure 5. Boot Memory Map
BUS REQUEST AND BUS GRANT
The ADSP-21992 can relinquish control of the data and address
buses to an external device. When the external device requires
access to the bus, it asserts the bus request (BR) signal. The (BR)
signal is arbitrated with core and peripheral requests. External
bus requests have the lowest priority. If no other internal
request is pending, the external bus request will be granted. Due
to synchronizer and arbitration delays, bus grants will be pro-
vided with a minimum of three peripheral clock delays. The
ADSP-21992 will respond to the bus grant by:
• Three-stating the data and address buses and the MS3–0,
BMS, IOMS, RD, and WR output drivers.
• Asserting the bus grant (BG) signal.
Rev. A | Page 6 of 60 | August 2007
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