ADSP-21992 Просмотр технического описания (PDF) - Analog Devices
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ADSP-21992 Datasheet PDF : 60 Pages
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ADSP-21992
INTERNAL MEMORY
FOUR INDEPENDENT BLOCKS
ADSP-219x DSP CORE
CACHE
64 ؋ 24-BIT
DAG1
DAG2
4 ؋ 4 ؋ 16 4 ؋ 4 ؋ 16
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
ADDRESS 24 BIT
DATA
ADDRESS 24 BIT
DATA
ADDRESS 16 BIT
DATA
ADDRESS 16 BIT
DATA
I/O ADDRESS 18
DM ADDRESS BUS 24
DMA CONNECT
DMA ADDRESS 24
PX
PM DATA BUS 24
DMA DATA 24
DATA
DM DATA BUS 16
REGISTER
FILE
I/O DATA 16
INPUT
REGISTERS
RESULT
REGISTERS
MULT 16 ؋ 16-BIT
BARREL
SHIFTER
ALU
I/O REGISTERS
(MEMORY-MAPPED)
CONTROL
STATUS
BUFFERS
JTAG
6
TEST AND
EMULATION
EXTERNAL PORT
ADDR BUS
MUX
20
DATA BUS
MUX
16
I/O PROCESSOR
EMBEDDED
CONTROL
PERIPHERALS
AND
COMMUNICATIONS
PORTS
DMA CONTROLLER
SYSTEM INTERRUPT PROGRAMMABLE TIMERS 3
CONTROLLER
FLAGS (16)
(3)
Figure 2. Block Diagram
an algebraic syntax for ease of coding and readability. A com-
prehensive set of development tools supports program
development.
The block diagram (Figure 2) shows the architecture of the
embedded SHARC core. It contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data from
the register file and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single cycle multiply, multiply/add, and multi-
ply/subtract operations. The MAC has two 40-bit accumulators,
which help with overflow. The shifter performs logical and
arithmetic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword and
block floating-point representations.
Register usage rules influence placement of input and results
within the computational units. For most operations, the data
registers of the computational units act as a data register file,
permitting any input or result register to provide input to any
unit for a computation. For feedback operations, the computa-
tional units let the output (result) of any unit be input to any
unit on the next cycle. For conditional or multifunction instruc-
tions, there are restrictions on which data registers may provide
inputs or receive results from each computational unit. For
more information, see the ADSP-2199x DSP Instruction Set
Reference.
A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou-
tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-21992 executes looped code
with zero overhead; no explicit jump instructions are required
to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four 16-bit
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is pre- or post-modified by the value of
one of four possible modify registers. A length value and base
address may be associated with each pointer to implement auto-
matic modulo addressing for circular buffers. Page registers in
the DAGs allow circular addressing within 64K word bound-
aries of each of the 256 memory pages, but these buffers may not
cross page boundaries. Secondary registers duplicate all the pri-
mary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
• Program memory address (PMA) bus
• Program memory data (PMD) bus
• Data memory address (DMA) bus
• Data memory data (DMD) bus
• Direct memory access address bus
• Direct memory access data bus
Rev. A | Page 4 of 60 | August 2007
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