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ADSP-21991BST

Mixed Signal DSP Controller

Analog Devices 

ADSP-21991

• Clocking: the SPORT can use an external serial clock or

generate its own in a wide range of frequencies down to

0 Hz.

• Word length: each SPORT section supports serial data

word lengths from three to sixteen bits that can be trans-

ferred either MSB first or LSB first.

• Framing: each SPORT section (receive and transmit) can

operate with or without frame synchronization signals for

each data-word; with internally generated or externally

generated frame signals; with active high or active low

frame signals; with either of two pulsewidths and frame

signal timing.

• Companding in hardware: each SPORT section can

perform A law and µ law companding according to

CCITT recommendation G.711.

• Direct Memory Access with single cycle overhead: using

the built-in DMA master, the SPORT can automatically

receive and/or transmit multiple memory buffers of data

with an overhead of only one DSP cycle per data-word.

The on-chip DSP via a linked list of memory space

resident DMA descriptor blocks can configure transfers

between the SPORT and memory space. This chained list

can be dynamically allocated and updated.

• Interrupts: each SPORT section (receive and transmit)

generates an interrupt upon completing a data-word

transfer, or after transferring an entire buffer or buffers if

DMA is used.

• Multichannel capability: The SPORT can receive and

transmit data selectively from channels of a serial bit

stream that is time division multiplexed into up to 128

channels. This is especially useful for T1 interfaces or as

a network communication scheme for multiple proces-

sors. The SPORTs also support T1 and E1 carrier

systems.

• Each SPORT channel (Tx and Rx) supports a DMA

buffer of up to eight, 16-bit transfers.

• The SPORT operates at a frequency of up to one-half the

clock frequency of the HCLK

• The SPORT is capable of UART software emulation.

Analog-to-Digital Conversion System

The ADSP-21991 contains a fast, high accuracy, multiple input

analog-to-digital conversion system with simultaneous sampling

capabilities. This A/D conversion system permits the fast,

accurate conversion of analog signals needed in high performance

embedded systems. Key features of the ADC system are:

• 14-bit Pipeline (6-Stage Pipeline) Flash Analog-to-

Digital Converter.

• 8 dedicated analog inputs.

• Dual channel simultaneous sampling capability.

• Programmable ADC clock rate to maximum of

HCLK،4.

• First channel ADC data valid approximately 375 ns after

CONVST (at 20 MSPS).

• All 8 inputs converted in approximately 725 ns (at

20 MSPS).

• 2.0 V peak-to-peak input voltage range.

• Multiple convert start sources.

• Internal or external Voltage Reference.

• Out of range detection.

• DMA capable transfers from ADC to memory.

The ADC system is based on a pipeline flash converter core, and

contains dual input sample-and-hold amplifiers so that simulta-

neous sampling of two input signals is supported. The ADC

system provides an analog input voltage range of 2.0 Vp-p and

provides 14-bit performance with a clock rate of up to HCLK،4.

The ADC system can be programmed to operate at a clock rate

that is programmable from HCLK⁄4 to HCLK⁄30, to a maximum

of 20 MHz (at 160 MHz CCLK rate).

The ADC input structure supports 8 independent analog inputs;

four of which are multiplexed into one sample-and-hold amplifier

(A_SHA) and 4 of which are multiplexed into the other sample-

and-hold amplifier (B_SHA).

At the 20 MHz sampling rate, the first data value is valid approx-

imately 375 ns after the Convert Start command. All 8 channels

are converted in approximately 725 ns.

The core of the ADSP-21991 provides 14-bit data such that the

stored data values in the ADC data registers are 14 bits wide.

Voltage Reference

The ADSP-21991 contains an onboard band gap reference that

can be used to provide a precise 1.0 V output for use by the A/D

system and externally on the VREF pin for biasing and level

shifting functions. Additionally, the ADSP-21991 may be con-

figured to operate with an external reference applied to the VREF

pin, if required.

PWM Generation Unit

Key features of the 3-phase PWM generation unit are:

• 16-bit, center based PWM generation unit

• Programmable PWM pulsewidth, with resolutions to

12.5 ns (at 80 MHz HCLK Rate)

• Single/double update modes

• Programmable dead time and switching frequency

• Twos complement implementation permits smooth tran-

sition into full ON and full OFF states

• Possibility to synchronize the PWM generation to an

external synchronization

• Special provisions for BDCM Operation (crossover and

output enable functions)

• Wide variety of special switched reluctance (SR)

operating modes

• Output polarity and clock gating control

• Dedicated asynchronous PWM shutdown signal

• Multiple shutdown sources, independently for each unit

–8–

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