ADSP-21991BST Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

ADSP-21991BST

Mixed Signal DSP Controller

Analog Devices 

ADSP-21991

INTERNAL MEMORY

FOUR INDEPENDENT BLOCKS

ADSP-219x DSP CORE

CACHE

64 ؋ 24-BIT

DAG1

DAG2

4 ؋ 4 ؋ 16 4 ؋ 4 ؋ 16

PROGRAM

SEQUENCER

PM ADDRESS BUS

24

ADDRESS 24 BIT

DATA

ADDRESS 24 BIT

DATA

ADDRESS 16 BIT

DATA

ADDRESS 16 BIT

DATA

I/O ADDRESS 18

DM ADDRESS BUS 24

DMA CONNECT

PX

PM DATA BUS 24

DMA ADDRESS 24

DMA DATA 24

DATA

DM DATA BUS 16

REGISTER

FILE

I/O DATA 16

INPUT

REGISTERS

RESULT

REGISTERS

MULT 16 ؋ 16-BIT

BARREL

SHIFTER

ALU

I/O REGISTERS

(MEMORY-MAPPED)

CONTROL

STATUS

BUFFERS

JTAG

6

TEST AND

EMULATION

EXTERNAL PORT

ADDR BUS

MUX

20

DATA BUS

MUX

16

I/O PROCESSOR

EMBEDDED

CONTROL

PERIPHERALS

AND

COMMUNICATIONS

PORTS

DMA CONTROLLER

SYSTEM INTERRUPT PROGRAMMABLE TIMERS 3

CONTROLLER

FLAGS (16)

(3)

Figure 1. Block Diagram

Efficient data transfer in the core is achieved with the use of

internal buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Direct Memory Access Address Bus

• Direct Memory Access Data Bus

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Boot memory space and I/O memory space also share the

external buses.

Program memory can store both instructions and data, permit-

ting the ADSP-21991 to fetch two operands in a single cycle, one

from program memory and one from data memory. The DSP

dual memory buses also let the embedded ADSP-219x core fetch

an operand from data memory and the next instruction from

program memory in a single cycle.

Memory Architecture

The ADSP-21991 provides 40K words of on-chip SRAM

memory. This memory is divided into three blocks: two

16K × 24-bit blocks (blocks 0 and 1) and one 8K × 16-bit block

(block 2). In addition, the ADSP-21991 provides a 4K × 24-bit

block of program memory boot ROM (that is reserved by ADI

for boot load routines). The memory map of the ADSP-21991

is illustrated in Figure 2.

As shown in Figure 2, the three internal memory RAM blocks

reside in memory page 0. The entire DSP memory map consists

of 256 pages (pages 0 to 255), and each page is 64K words long.

External memory space consists of four memory banks

(banks3–0) and supports a wide variety of memory devices. Each

bank is selectable using unique memory select lines (MS3–0) and

has configurable page boundaries, wait states, and wait state

modes. The 4K words of on-chip boot ROM populates the top

of page 255, while the remaining 254 pages are addressable off-

chip. I/O memory pages differ from external memory in that they

are 1K word long, and the external I/O pages have their own select

pin (IOMS). Pages 31–0 of I/O memory space reside on-chip and

–4–

REV. 0

Share Link: