ADSP-2188M(RevPrA) Просмотр технического описания (PDF) - Analog Devices

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ADSP-2188M
(Rev.:RevPrA)

DSP Microcomputer

Analog Devices 

April 1999

ADSP-2188M Preliminary Data Sheet

For current information contact Analog Devices at (781) 461-3881

Serial Ports

The ADSP-2188M incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for

serial communications and multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2188M SPORTs. For additional information on

Serial Ports, refer to the ADSP-2100 Family User’s Manual.

• SPORTs are bidirectional and have a separate, double-buffered transmit and receive section.

• SPORTs can use an external serial clock or generate their own serial clock internally.

• SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless

mode or with frame synchronization signals internally or externally generated. Frame sync signals

are active high or inverted, with either of two pulse widths and timings.

• SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and µ-law

companding according to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique interrupts on completing a data word

transfer.

• SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per

data word. An interrupt is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-

division multiplexed, serial bitstream.

• SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the Flag In and

Flag Out signals. The internally generated serial clock may still be used in this configuration.

Pin Descriptions

The ADSP-2188M will be available in a 100-lead LQFP package. In order to maintain maximum

functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and

external bus pins have dual, multiplexed functionality. The external bus pins are configured during

RESET only, while serial port pins are software configurable during program execution. Flag and

interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is

reconfigurable, the default state is shown in plain text; alternate functionality is shown in italics.

Common Mode Pins

Pin Name(s)

RESET

BR

BG

BGH

DMS

PMS

IOMS

# of I/O

Pins

1I

1I

1O

1O

1O

1O

1O

Function

Processor Reset Input

Bus Request Input

Bus Grant Output

Bus Grant Hung Output

Data Memory Select Output

Program Memory Select Output

Memory Select Output

6

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

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