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ADSP-2188M(RevPrA) Просмотр технического описания (PDF) - Analog Devices

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Компоненты Описание
производитель
ADSP-2188M
(Rev.:RevPrA)
ADI
Analog Devices ADI
ADSP-2188M Datasheet PDF : 52 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
April 1999
ADSP-2188M Preliminary Data Sheet
For current information contact Analog Devices at (781) 461-3881
ARCHITECTURE OVERVIEW
The ADSP-2188M instruction set provides flexible data moves and multifunction (one or two data
moves with a computation) instructions. Every instruction can be executed in a single processor cycle.
The ADSP-2188M assembly language uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program development.
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Figure 1 FUNCTIONAL BLOCK DIAGRAM
Figure 1 is an overall block diagram of the ADSP-2188M. The processor contains three independent
computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational
units process 16-bit data directly and have provisions to support multiprecision computations. The
ALU performs a standard set of arithmetic and logic operations; division primitives are also supported.
The MAC performs single-cycle multiply, multiply/add and multiply/subtract operations with 40 bits
of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization,
and derive exponent operations.
The shifter can be used to efficiently implement numeric format control including multi-word and
block floating-point representations.
The internal result (R) bus connects the computational units so that the output of any unit may be the
input of any unit on the next cycle.
A powerful program sequencer and two dedicated data address generators ensure efficient delivery of
operands to these computational units. The sequencer supports conditional jumps, subroutine calls and
returns in a single cycle. With internal loop counters and loop stacks, the ADSP-2188M executes
looped code with zero overhead; no explicit jump instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from
data memory and program memory). Each DAG maintains and updates four address pointers.
Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one
4
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrA

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