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ADSP-2184L

DSP Microcomputer

Analog Devices 

ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L

because there are no internal pull-ups to guarantee their state

during prolonged three-state conditions resulting from typical

EZ-ICE debugging sessions. These resistors may be removed

when the EZ-ICE is not being used.

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some

system signals changes. Design the system to be compatible with

the following system interface signal changes introduced by the

EZ-ICE board:

• EZ-ICE emulation introduces an 8 ns propagation

delay between the target circuitry and the DSP on the

RESET signal.

• EZ-ICE emulation introduces an 8 ns propagation

delay between the target circuitry and the DSP on the BR

signal.

• EZ-ICE emulation ignores RESET and BR, when

single-stepping.

• EZ-ICE emulation ignores RESET and BR when in Emula-

tor Space (DSP halted).

• EZ-ICE emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of

the DSP’s external memory bus only if bus grant (BG) is

asserted by the EZ-ICE board’s DSP.

ADDITIONAL INFORMATION

This data sheet provides a general overview of ADSP-218xL

series functionality. For additional information on the architec-

ture and instruction set of the processor, refer to the ADSP-218x

DSP Hardware Reference and the ADSP-218x DSP Instruction

Set Reference.

Rev. C | Page 16 of 48 | January 2008

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