ADSP-2184L(Rev0) Просмотр технического описания (PDF) - Analog Devices
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ADSP-2184L Datasheet PDF : 31 Pages
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ADSP-2184L
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 16K × 8 pages.
The byte memory space on the ADSP-2184L supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
The BDMA circuit supports four different data formats, that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses is determined from the byte memory space to
build the word size selected. Table V shows the data formats sup-
ported by the BDMA circuit.
Table V.
BTYPE
00
01
10
11
Internal
Memory Space
Program Memory
Data Memory
Data Memory
Data Memory
Word Size
24
16
8
8
Alignment
Full Word
Full Word
MSBs
LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address for
the on-chip memory involved with the transfer. The 14-bit BEAD
register specifies the starting address for the external byte memory
space. The 8-bit BMPAGE register specifies the starting page for
the external byte memory space. The BDIR register field selects
the direction of the transfer. Finally the 14-bit BWCOUNT
register specifies the number of DSP words to transfer and
initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory, regardless of the values of
Mode B, PMOVLAY or DMOVLAY.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory
accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor and start execution at address 0 when
the BDMA accesses have completed.
Composite Memory Select (CMS)
The ADSP-2184L has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS), but can combine their
functionality.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory and use either DMS or PMS as the additional
address bit.
The CMS pin functions as the other memory select signal, with
the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits, except the BMS
bit, default to 1 at reset.
Internal Memory DMA Port (IDMA Port; Host Memory Mode)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2184L. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write directly to the DSP’s
memory-mapped control registers.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
pletely asynchronous and can be written to while the ADSP-
2184L is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This in-
creases throughput as the address does not have to be sent for
each memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the IDMA address latch signal
(IAL) or the missing edge of the IDMA select signal (IS) latches
this value into the IDMAA register.
Once the address is stored, data can then either be read from or
written to the ADSP-2184L’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2184L that a particular
REV. 0
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