ADSP-21469KBCZ-4 Просмотр технического описания (PDF) - Analog Devices

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ADSP-21469KBCZ-4

SHARC Processor

Analog Devices 

ADSP-21467/ADSP-21469

Note that the external memory bank addresses shown are for

normal-word (32-bit) accesses. If 48-bit instructions, as well as

32-bit data, are both placed in the same external memory bank,

care must be taken while mapping them to avoid overlap.

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, Flash, and EPROM, as well

as I/O devices that interface with standard memory control

lines. Bank 0 occupies a 2M word window and banks 1, 2, and 3

occupy a 4M word window in the processor’s address space but,

if not fully populated, these windows are not made contiguous

by the memory controller logic.

External Port Throughput

The throughput for the external port, based on a 400 MHz

clock, is 66M bytes/s for the AMI and 800M bytes/s for DDR2.

Link Ports

Two 8-bit wide link ports can connect to the link ports of other

DSPs or peripherals. Link ports are bidirectional ports having

eight data lines, an acknowledge line, and a clock line. Link

ports can operate at a maximum frequency of 166 MHz.

MediaLB

The automotive model has a MLB interface which allows the

processors to function as a media local bus device. It includes

support for both 3-pin and 5-pin media local bus protocols. It

supports speeds up to 1024 FS (49.25M bits/sec, FS = 48.1 kHz)

and up to 31 logical channels, with up to 124 bytes of data per

media local bus frame.

The MLB interface supports MOST25 and MOST50 data rates.

The isochronous mode of transfer is not supported.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM

waveforms. In addition, it can generate complementary signals

on two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms). The PWM generator is capable of operating in two

distinct modes while generating center-aligned PWM wave-

forms: single update mode or double update mode.

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to

connect various peripherals to any of the DAI pins

(DAI_P20–1).

Programs make these connections using the signal routing unit

(SRU), shown in Figure 1 on Page 1.

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with noncon-

figurable signal paths.

The DAI includes the peripherals described in the following

sections.

Serial Ports

The processors feature eight synchronous serial ports that pro-

vide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Serial ports can support up to 16 transmit or 16 receive DMA

channels of audio data when all eight SPORTs are enabled, or

four full duplex TDM streams of 128 channels per frame.

The serial ports operate at a maximum data rate of fPCLK/4.

Serial port data can be automatically transferred to and from

on-chip memory/external memory via dedicated DMA chan-

nels. Each of the serial ports can work in conjunction with

another serial port to provide TDM support. One SPORT pro-

vides two transmit signals while the other SPORT provides the

two receive signals. The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I2S mode

• Packed I2S mode

• Left-justified mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the receiver/

transmitter can be formatted as left justified, I2S or right justi-

fied with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources, such as the

SPORTs, external pins, and the precision clock generators

(PCGs), and are controlled by the SRU control registers.

Rev. B | Page 8 of 76 | March 2013

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