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ADSP-21469BBCZ-3

SHARC Processor

Analog Devices 

FAMILY PERIPHERAL ARCHITECTURE

The processors contain a rich set of peripherals that support a

wide variety of applications including high quality audio, medi-

cal imaging, communications, military, test equipment, 3D

graphics, speech recognition, motor control, imaging, and other

applications.

External Port

The external port interface supports access to the external mem-

ory through core and DMA accesses. The external memory

address space is divided into four banks. Any bank can be pro-

grammed as either asynchronous or synchronous memory. The

external ports are comprised of the following modules.

• An Asynchronous Memory Interface which communicates

with SRAM, Flash, and other devices that meet the stan-

dard asynchronous SRAM access protocol. The AMI

supports 2M words of external memory in bank 0 and 4M

words of external memory in bank 1, bank 2, and bank 3.

• A DDR2 DRAM controller. External memory devices up to

2 Gbits in size can be supported.

• Arbitration logic to coordinate core and DMA transfers

between internal and external memory over the external

port.

External Memory

The external port on the processors provide a high perfor-

mance, glueless interface to a wide variety of industry-standard

memory devices. The external port may be used to interface to

synchronous and/or asynchronous memory devices through the

use of its separate internal DDR2 memory controller. The 16-bit

DDR2 DRAM controller connects to industry-standard syn-

chronous DRAM devices, while the second 8-bit asynchronous

memory controller is intended to interface to a variety of mem-

ory devices. Four memory select pins enable up to four separate

devices to coexist, supporting any desired combination of syn-

chronous and asynchronous device types. Non-DDR2 DRAM

external memory address space is shown in Table 4.

Table 4. External Memory for Non-DDR2 DRAM Addresses

Bank

Bank 0

Bank 1

Bank 2

Bank 3

Size in Words Address Range

2M

0x0020 0000 – 0x003F FFFF

4M

0x0400 0000 – 0x043F FFFF

4M

0x0800 0000 – 0x083F FFFF

4M

0x0C00 0000 – 0x0C3F FFFF

SIMD Access to External Memory

The DDR2 controller supports SIMD access on the 64-bit EPD

(external port data bus) which allows to access the complemen-

tary registers on the PEy unit in the normal word space (NW).

This improves performance since there is no need to explicitly

load the complimentary registers as in SISD mode.

ADSP-21467/ADSP-21469

VISA and ISA Access to External Memory

The DDR2 controller also supports VISA code operation which

reduces the memory load since the VISA instructions are com-

pressed. Moreover, bus fetching is reduced because, in the best

case, one 48-bit fetch contains three valid instructions. Code

execution from the traditional ISA operation is also supported.

Note that code execution is only supported from bank 0 regard-

less of VISA/ISA. Table 5 shows the address ranges for

instruction fetch in each mode.

Table 5. External Bank 0 Instruction Fetch

Access Type

ISA (NW)

VISA (SW)

Size in Words Address Range

4M

0x0020 0000 – 0x005F FFFF

10M

0x0060 0000 – 0x00FF FFFF

Shared External Memory

The processors support connection to common shared external

DDR2 memory with other ADSP-2146x processors to create

shared external bus processor systems. This support includes:

• Distributed, on-chip arbitration for the shared external bus

• Fixed and rotating priority bus arbitration

• Bus time-out logic

• Bus lock

Multiple processors can share the external bus with no addi-

tional arbitration logic. Arbitration logic is included on-chip to

allow the connection of up to two processors. Table 10 on

Page 14 provides descriptions of the pins used in multiprocessor

systems.

DDR2 Support

The processors support a 16-bit DDR2 interface operating at a

maximum frequency of half the core clock. Execution from

external memory is supported. External memory devices up to

2 Gbits in size can be supported.

DDR2 DRAM Controller

The DDR2 DRAM controller provides a 16-bit interface to up to

four separate banks of industry-standard DDR2 DRAM devices.

Fully compliant with the DDR2 DRAM standard, each bank can

have its own memory select line (DDR2_CS3 – DDR2_CS0),

and can be configured to contain between 32 Mbytes and

256 Mbytes of memory. DDR2 DRAM external memory

address space is shown in Table 6.

A set of programmable timing parameters is available to config-

ure the DDR2 DRAM banks to support memory devices.

Table 6. External Memory for DDR2 DRAM Addresses

Bank

Bank 0

Bank 1

Bank 2

Bank 3

Size in Words Address Range

62M

0x0020 0000 – 0x03FF FFFF

64M

0x0400 0000 – 0x07FF FFFF

64M

0x0800 0000 – 0x0BFF FFFF

64M

0x0C00 0000 – 0x0FFF FFFF

Rev. B | Page 7 of 76 | March 2013

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