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ADSP-21469BBC-3

SHARC Processor

Analog Devices 

ADSP-21467/ADSP-21469

Table 10. Pin Descriptions (Continued)

Name

Type

State During/ After

Reset

Description

RESET

I

Processor Reset. Resets the processor to a known state. Upon deassertion, there is a

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program

execution from the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

RESETOUT/

RUNRSTIN

I/O (ipu)

Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also

has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL

register. For more information, see the ADSP-214xx SHARC Processor Hardware

Reference.

BOOT_CFG2–0 I

Boot Configuration Select. These pins select the boot mode for the processor. The

BOOT_CFG pins must be valid before RESET (hardware and software) is de-asserted.

The following symbols appear in the Type column of Table 10: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.

To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be

enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–

63 k. The range of an ipd resistor can be between 31 k–85 k. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at

typical conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.

Table 11. Pin List, Power and Ground

Name

VDD_INT

VDD_EXT

VDD_A

VDD_THD

Type

P

P

P

P

VDD_DDR21

P

VREF

P

GND

G

AGND

G

1 Applies to DDR2 signals.

Description

Internal Power

External Power

Analog Power for PLL

Thermal Diode Power; if thermal diode is not used then this pin can be

left floating

DDR2 Interface Power

DDR2 Input Voltage Reference

Ground

Analog Ground

Rev. B | Page 18 of 76 | March 2013

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