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ADSP-21469BBC-3

SHARC Processor

Analog Devices 

ADSP-21467/ADSP-21469

Table 10. Pin Descriptions

Name

Type

State During/ After

Reset

Description

AMI_ADDR23–0 I/O/T (ipu)

High-Z/

driven low (boot)

External Address. The processor outputs addresses for external memory and periph-

erals on these pins. The data pins can be multiplexed to support the PDAP (I) and PWM

(O). After reset, all AMI_ADDR23–0 pins are in external memory interface mode and

FLAG(0–3) pins are in FLAGS mode (default). When configured in the IDP_PDAP_CTL

register, IDP channel 0 scans the AMI_ADDR23–0 pins for parallel input data. Unused

AMI pins can be left unconnected.

AMI_DATA7–0 I/O/T (ipu) High-Z

External Data. The data pins can be multiplexed to support the external memory

interface data (I/O), the PDAP (I), FLAGS (I/O) and PWM (O). After reset, all AMI_DATA

pins are in EMIF mode and FLAG(0-3) pins are in FLAGS mode (default). Unused AMI

pins can be left unconnected.

AMI_ACK

I (ipu)

Memory Acknowledge (AMI_ACK). External devices can deassert AMI_ACK (low) to

add wait states to an external memory access. AMI_ACK is used by I/O devices,

memory controllers, or other peripherals to hold off completion of an external

memory access. Unused AMI pins can be left unconnected.

AMI_MS0–1

O/T (ipu)

High-Z

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-

sponding banks of external memory on the AMI interface. The AMI_MS1-0 lines are

decoded memory address lines that change at the same time as the other address

lines. When no external memory access is occurring the AMI_MS1-0 lines are inactive;

they are active however when a conditional memory access instruction is executed,

when the condition evaluates as true. Unused AMI pins can be left unconnected. The

AMI_MS1 pin can be used in EPORT/FLASH boot mode. For more information, see the

ADSP-214xx SHARC Processor Hardware Reference.

AMI_RD

O/T (ipu)

High-Z

AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word from

external memory.

AMI_WR

O/T (ipu)

High-Z

External Port Write Enable. AMI_WR is asserted when the processor writes a word

to external memory.

FLAG[0]/IRQ0 I/O (ipu)

FLAG[0] INPUT

FLAG0/Interrupt Request0.

FLAG[1]/IRQ1 I/O (ipu)

FLAG[1] INPUT

FLAG1/Interrupt Request1.

FLAG[2]/IRQ2/

AMI_MS2

I/O (ipu)

FLAG[2] INPUT

FLAG2/Interrupt Request2/Async Memory Select2.

FLAG[3]/TMREXP/ I/O (ipu)

AMI_MS3

FLAG[3] INPUT

FLAG3/Timer Expired/Async Memory Select3.

The following symbols appear in the Type column of Table 10: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,

O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.

The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.

To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be

enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–

63 k. The range of an ipd resistor can be between 31 k–85 k. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at

typical conditions the voltage is in the range of 2.3 V to 2.7 V.

In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.

Rev. B | Page 14 of 76 | March 2013

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