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ADSP-21375KSZ-ENG

SHARC® Processor

Analog Devices 

ADSP-21375

ports are made up of two data lines, a clock and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Serial ports are enabled via eight programmable and simulta-

neous receive or transmit pins that support up to 16 transmit or

16 receive channels of audio data when all four SPORTS are

enabled, or four full duplex TDM streams of 128 channels per

frame.

The serial ports operate at a maximum data rate of 50M bits/s.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode with support for Packed I2S

mode

• I2S mode

• Packed I2S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Each of the serial ports supports the left-justified sample pair

and I2S protocols (I2S is an industry standard interface com-

monly used by audio codecs, ADCs and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I2S channels (using two stereo

devices) per serial port, with a maximum of up to 32 I2S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I2S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional μ-law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

The serial ports also contain frame sync error detection logic

where the serial ports detect frame syncs that arrive early (for

example frame syncs that arrive while the transmission/recep-

tion of the previous word is occurring). All the serial ports also

share one dedicated error interrupt.

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two

serial peripheral interface ports (SPI), one universal asynchro-

nous receiver-transmitter (UART), 12 flags, a two wire interface

(TWI), and two general-purpose timers.

Preliminary Technical Data

Serial Peripheral (Compatible) Interface

The ADSP-21375 SHARC processor contains two serial periph-

eral interface ports (SPIs). The SPI is an industry standard

synchronous serial link, enabling the ADSP-21375 SPI compati-

ble port to communicate with other SPI compatible devices. The

SPI consists of two data pins, one device select pin, and one

clock pin. It is a full-duplex synchronous serial interface, sup-

porting both master and slave modes. The SPI port can operate

in a multimaster environment by interfacing with up to four

other SPI compatible devices, either acting as a master or slave

device. The ADSP-21375 SPI compatible peripheral implemen-

tation also features programmable baud rate and clock phase

and polarities. The ADSP-21375 SPI compatible port uses open

drain drivers to support a multimaster configuration and to

avoid data contention.

UART Port

The ADSP-21375 processor provides a full-duplex Universal

Asynchronous Receiver/Transmitter (UART) port, which is

fully compatible with PC-standard UARTs. The UART port

provides a simplified UART interface to other peripherals or

hosts, supporting full-duplex, DMA-supported, asynchronous

transfers of serial data. The UART also has multiprocessor com-

munication capability using 9-bit address detection. This allows

it to be used in multidrop networks through the RS-485 data

interface standard. The UART port also includes support for 5

to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The

UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (fSCLK/ 1,048,576) to

(fSCLK/16) bits per second.

• Supporting data formats from 7 to12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

where the 16-bit UART_Divisor comes from the DLH register

(most significant 8 bits) and DLL register (least significant

8 bits).

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

Rev. PrB | Page 8 of 42 | December 2005

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