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ADSP-21375KSZ-ENG

SHARC® Processor

Analog Devices 

ADSP-21375

Preliminary Technical Data

Table 2. ADSP-21375 Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Long Word (64 bits)

Extended Precision Normal or

Instruction Word (48 bits)

Normal Word (32 bits)

BLOCK 0 ROM

0x0004 0000–0x0004 3FFF

BLOCK 0 ROM

0x0008 0000–0x0008 5554

BLOCK 0 ROM

0x0008 0000–0x0008 7FFF

Reserved

0x0004 4000–0x0004 BFFF

Reserved

0x0008 5555–0x0008 FFFF

Reserved

0x00088000–0x00097FFF

BLOCK 0 RAM

0x0004 C000–0x0004C7FF

BLOCK 0 RAM

0x0009 0000–0x0009 0AAA

BLOCK 0 RAM

0x0009 8000–0x0009 8FFF

Reserved

0x0004 C800–0x0004 FFFF

Reserved

0x0009 0AAB–0x0009 5554

Reserved

0x0009 9000–0x0009 FFFF

BLOCK 1 ROM

0x0005 0000–0x0005 3FFF

BLOCK 1 ROM

0x000A 0000–0x000A 5554

BLOCK 1 ROM

0x000A 0000–0x000A 7FFF

Reserved

0x0005 4000–0x0005 BFFF

Reserved

0x000A 5555–0x000A FFFF

Reserved

0x000A 8000–0x000B 7FFF

BLOCK 1 RAM

0x0005 C000–0x0005 C7FF

BLOCK 1 RAM

0x000B 0000–0x000B 0AAA

BLOCK 1 RAM

0x000B 8000–0x000B 8FFF

Reserved

Reserved

0x0005 C8000–0x0005 FFFF 0x000B 0AAB–0X000B 5554

Reserved

0x000B 9000–0x000B FFFF

BLOCK 2 RAM

0x0006 0000–0x0006 07FF

BLOCK 2 RAM

0x000C 0000–0x000C 0AAA

BLOCK 2 RAM

0X000C 0000 - 0X000C 3FFF

Reserved

0x0006 0800–0x0006 1FFF

Reserved

0x000C 0AAB–0x000C 3FFF

Reserved

0x000C 1000–0x000C 1FFF

Reserved

0x0006 2000–0x0006 FFFF

Reserved

0x000D 4000–0x000D 5554

Reserved

0x000C 4000–0x000D FFFF

BLOCK 3 RAM

0x0007 0000–0x0007 07FF

BLOCK 3 RAM

0x000E 0000–0x000E 0AAA

BLOCK 3 RAM

0x000E 0000–0x000E 0FFF

Reserved

0x0007 0800–0x0007 1FFF

Reserved

0x000E 0AAB–0x000C 3FFF

Reserved

0x000E 1000–0x000E 3FFF

Reserved

0x0007 2000–0x0007 FFFF

Reserved

0x000F 4000–0x000F 5554

Reserved

0x000E 4000–0x000F FFFF

Short Word (16 bits)

BLOCK 0 ROM

0x0010 0000–0x0010 FFFF

Reserved

0x0011 0000–0x0012 FFFF

BLOCK 0 RAM

0x0013 0000–0x0013 1FFF

Reserved

0x0013 2000–0x0013 FFFF

BLOCK 1 ROM

0x0014 0000–0x0014 FFFF

Reserved

0x0015 0000–0x0016 FFFF

BLOCK 1 RAM

0x0017 0000–0x0017 1FFF

Reserved

0x0017 2000–0x0017 FFFF

BLOCK 2 RAM

0x0018 0000–0x0018 1FFF

Reserved

0x0018 2000–0x0018 7FFF

Reserved

0x0018 8000–0x001B FFFF

BLOCK 3 RAM

0x001C 0000–0x001C 1FFF

Reserved

0x001C 2000–0x001C 7FFF

Reserved

0x001C 8000–0x001F FFFF

Table 3. External Memory for Non SDRAM Addresses

Bank

Bank 0

Bank 1

Bank 2

Bank 3

Size in

words

14M

16M

16M

16M

Address Range

0x0020 0000 – 0x00FF FFFF

0x0400 0000 – 0x04FF FFFF

0x0800 0000 – 0x08FF FFFF

0x0C00 0000 – 0x0CFF FFFF

SDRAM Controller

The SDRAM controller provides an interface to up to four sepa-

rate banks of industry-standard SDRAM devices or DIMMs, at

speeds up to fSCLK. Fully compliant with the SDRAM standard,

each bank can has it's own memory select line (MS0–MS3), and

can be configured to contain between 16M bytes and

128M bytes of memory. SDRAM external memory address

space is shown in Table 4.

The controller maintains all of the banks as a contiguous

address space so that the processor sees this as a single address

space, even if different size devices are used in the different

banks.

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. The

memory banks can be configured as 16 bits wide.

Rev. PrB | Page 6 of 42 | December 2005

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