ADSP-21365(RevA) Просмотр технического описания (PDF) - Analog Devices

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производитель

ADSP-21365
(Rev.:RevA)

SHARC® Processor

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

ADDRESS DATA PINS AS FLAGS

To use these pins as flags (FLAGS15–0) set (=1) Bit 20 of the

SYSCTL register to disable the parallel port. Then set (=1)

Bits 22 to 25 in the SYSCTL register accordingly.

Table 5. AD15–0 to Flag Pin Mapping

AD Pin

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

Flag Pin

FLAG8

FLAG9

FLAG10

FLAG11

FLAG12

FLAG13

FLAG14

FLAG15

AD Pin

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

Flag Pin

FLAG0

FLAG1

FLAG2

FLAG3

FLAG4

FLAG5

FLAG6

FLAG7

ADDRESS/DATA MODES

The following table shows the functionality of the AD pins for

8-bit and 16-bit transfers to the parallel port. For 8-bit data

transfers, ALE latches Address Bits A23–A8 when asserted, fol-

lowed by Address Bits A7–A0 and Data Bits D7–D0 when

deasserted. For 16-bit data transfers, ALE latches Address Bits

A15–A0 when asserted, followed by Data Bits D15–D0 when

deasserted.

Table 6. Address/Data Mode Selection

PP Data

Mode

8-bit

8-bit

16-bit

16-bit

ALE

Asserted

Deasserted

Asserted

Deasserted

AD7–AD0

Function

A15–A8

D7–D0

A7–A0

D7–D0

AD15–AD8

Function

A23–A16

A7–A0

A15–A8

D15–D8

BOOT MODES

Table 7. Boot Mode Selection

BOOTCFG1–0

00

01

10

Booting Mode

SPI Slave Boot

SPI Master Boot

Parallel Port Boot via EPROM

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 6 on Page 18.

Table 8. Core Instruction Rate/CLKIN Ratio Selection

CLKCFG1–0

00

01

10

Core to CLKIN Ratio

6:1

32:1

16:1

Rev. A | Page 15 of 52 | December 2006

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