ADP3110 Просмотр технического описания (PDF) - ON Semiconductor

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ADP3110

Dual Bootstrapped, 12 V MOSFET Driver with Output Disable

ON Semiconductor 

ADP3110

APPLICATION INFORMATION

SUPPLY CAPACITOR SELECTION

For the supply input (VCC) of the ADP3110, a local bypass

capacitor is recommended to reduce the noise and to supply

some of the peak currents drawn. Use a 4.7 µF, low ESR

capacitor. Multilayer ceramic chip (MLCC) capacitors provide

the best combination of low ESR and small size. Keep the

ceramic capacitor as close as possible to the ADP3110.

BOOTSTRAP CIRCUIT

The bootstrap circuit uses a charge storage capacitor (CBST1) and

a diode, as shown in Figure 1. These components can be

selected after the high-side MOSFET is chosen. The bootstrap

capacitor must have a voltage rating that is able to handle twice

the maximum supply voltage. A minimum 50 V rating is

recommended. The capacitor values are determined using the

following equations:

C BST1

+ C BST2

= 10 × QGATE

VGATE

(1)

C BST1

= VGATE

(2)

C BST1 + C BST 2 VCC − VD

where:

QGATE is the total gate charge of the high-side MOSFET at VGATE.

VGATE is the desired gate drive voltage (usually in the range of

5 V to 10 V, 7 V being typical).

VD is the voltage drop across D1.

Rearranging Equation 1 and Equation 2 to solve for CBST1 yields

C

BST

1

=

10

×

QGATE

VCC − VD

(3)

CBST2 can then be found by rearranging Equation 1

C

BST

2

=

10

×

QGATE

VGATE

− C BST1

(4)

For example, an NTD60N02 has a total gate charge of about

12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 1 V, we find

CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic

capacitors should be used.

RBST is used for slew rate limiting to minimize the ringing at the

switch node. It also provides peak current limiting through D1.

An RBST value of 1.5 Ω to 2.2 Ω is a good choice. The resistor

needs to be able to handle at least 250 mW due to the peak

currents that flow through it.

A small signal diode can be used for the bootstrap diode due to

the ample gate drive voltage supplied by VCC. The bootstrap

diode must have a minimum 15 V rating to withstand the

maximum supply voltage. The average forward current can be

estimated by

I F(AVG) = QGATE × f MAX

(5)

where fMAX is the maximum switching frequency of the

controller.

The peak surge current rating should be calculated by

I F(PEAK )

=

VCC −VD

RBST

(6)

MOSFET SELECTION

When interfacing the ADP3110 to external MOSFETs, the

designer should be aware of a few considerations. These help to

make a more robust design that minimizes stresses on both the

driver and MOSFETs. These stresses include exceeding the

short-time duration voltage ratings on the driver pins as well as

the external MOSFET.

It is also highly recommended to use the Boot-Snap circuit to

improve the interaction of the driver with the characteristics of

the MOSFETs. If a simple bootstrap arrangement is used, make

sure to include a proper snubber network on the SW node.

High-Side (Control) MOSFETs

The high-side MOSFET is usually selected to be high speed to

minimize switching losses (see any ADI Flex-Mode™ controller

data sheet for more details on MOSFET losses). This usually

implies a low gate resistance and low input capacitance/charge

device. Yet, there is also a significant source lead inductance

that can exist (this depends mainly on the MOSFET package; it

is best to contact the MOSFET vendor for this information).

The ADP3110 DRVH output impedance and the external

MOSFETs’ input resistance determine the rate of charge delivery

to the MOSFETs’ gate capacitance which, in turn, determines

the switching times of the MOSFETs. A large voltage spike can

be generated across the source lead inductance when the high-

side MOSFETs switch off, due to large currents flowing in the

MOSFETs during switching (usually larger at turn off due to

ramping of the current in the output inductor). This voltage

spike occurs across the internal die of the MOSFETs and can

lead to catastrophic avalanche. The mechanisms involved in this

avalanche condition can be referenced in literature from the

MOSFET suppliers.

Rev. 2 | Page 8 of 11 | www.onsemi.com

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