ADP3110 Просмотр технического описания (PDF) - ON Semiconductor

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ADP3110

Dual Bootstrapped, 12 V MOSFET Driver with Output Disable

ON Semiconductor 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BST 1

8 DRVH

IN 2 ADP3110 7 SW

OD 3 TOP VIEW 6 PGND

VCC 4 (Not to Scale) 5 DRVL

Figure 2. 8-Lead SOIC_N Pin Configuration

ADP3110

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this

bootstrapped voltage for the high-side MOSFET as it is switched.

2

IN

Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin

low turns on the low-side driver; pulling it high turns on the high-side driver.

3

OD

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

4

VCC

Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.

5

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

6

PGND

Power Ground. This pin should be closely connected to the source of the lower MOSFET.

7

SW

Switch Node Connection. This pin is connected to the buck-switching node, close to the upper MOSFET’s

source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage

to prevent turn-on of the lower MOSFET until the voltage is below ~1 V.

8

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.

Rev. 2 | Page 5 of 11 | www.onsemi.com

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