ADP3088(RevC) Просмотр технического описания (PDF) - Analog Devices
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ADP3088 Datasheet PDF : 16 Pages
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ADP3088
where ⌬VR is the tolerable ripple voltage. However, this constraint
is rarely relevant, since the typical capacitance requirement is
Returning to constraints for choosing the output capacitor for
digital loads, another criterion for ensuring sufficient output
driven more by dynamic response requirements than by ripple
capacitance applies.
concerns. In a typical application circuit, a 10 mF capacitor
produces a capacitive output voltage ripple component of only
about 2 mV. 10 mF is usually sufficient for applications that do not
impose particularly high frequency load transients, and imposes
additional constraints that are elaborated upon in the next section.
CO
>
DIO2
2DVO
ÈdIL
Í
ÎÍ
dt
˘
MIN ˙
˚˙
(13)
Load Characterization
Optimization of the compensation, as well as the output filter,
where DIO is the maximum high frequency load step. It should
be noted that the formula results strictly from the physical
requires some knowledge of a fundamental characteristic of the limitation of the output filter; the compensation must also be
load. Qualitatively, there are two types of loads with which we
optimized to maximize the response of the control loop to avoid
are concerned: fast slew rate and slow slew rate. These slew
substantial additional output voltage deviation. The formula
rates are assessed with respect to the minimum (absolute)
inductor (current) slew rate, as given by
ÈÎÍÍÊËÁ
dI L
dt
ˆ
¯˜
,
MIN
˘
˚˙˙
=
<
ÏÌVIN (
Ó
MIN ) - VSW
LMAX
- VO
and
VO + VF
LMAX
¸˝˛ (12)
E where the < sign indicates a selection of whichever bracket term
is lower.
If the slew rate of the load is fast compared to the minimum
T inductor slew rate, then the ability of the power converter to
contain the output voltage deviation following a load change is
limited not only by the response of the control loop, i.e., by its
speed to demand zero or maximum duty ratio from the modulator,
E but by the power stage as well. In such a case, beginning with
the recognition that output voltage deviation would be substantial
even if the loop response were instantaneous, it can be shown
that one can achieve better overall voltage containment by
L degenerating the dc loop gain. As a technical matter, it should be
noted that there will always be some minimum output voltage
deviation downward due to a load step even if the inductor slew is
as fast as the load slew rate. During a switching cycle, the modula-
O tor latches its “decision” to turn off the switch. It cannot rescind
that decision, but must instead wait for the next clock cycle to
turn on the switch again and begin slewing the inductor current
upward. This is only a second-order consideration.
S Slow slew rate loads may be referred to simply as conventional
loads, since these have been the more prevalent type of load.
Optimally compensating a conventional load is synonymous
with small signal ac considerations; the objective is to maximize
B the ac gain up to the crossover frequency, ensure sufficient
phase margin at the unity gain crossover frequency, and keep
the gain rolling off at higher frequencies to avoid gain margin
problems.
O Fast slew rate loads may be referred to as digital loads since,
might also be written to describe a maximum inductance for a
given capacitance, but it is generally better practice to choose
the inductor first and add capacitance as needed.
The impedance of the output capacitor together with a digital
load also creates some limiting considerations. Series resistance
(ESR) rather than capacitance can be a dominant design
consideration with non-MLC capacitors. If the load is essentially
digital, then the dynamic deviation of the output voltage cannot
be limited to any better than the dynamic load current step
times the ESR. In a formula,
DVO ≥ DIO ¥ ESR
(14)
In such a case, it is often important to choose a capacitor that
controls the ESR to a sufficiently small value. MLC capacitors are
often chosen to practically eliminate the consideration of ESR
entirely.
Closing the Loop—Compensation
The factors determining the response of the power converter
include the feedback input resistor divider, a lead network if
applicable, the transconductance of the error amplifier, its
frequency response limitation (i.e., as adequately modeled by a
capacitance from output to ground), its external termination
impedance (i.e., the compensation that may or may not include
dc feedback), the modulator transconductance, and the power
converter’s termination impedance (i.e., the output capacitor
and load resistance).
Since the ADP3088 has a current-controlled loop, the particular
inductor value does not by first-order consideration affect small
signal stability. However, slew rate limitations, as discussed
earlier, a large signal limitation consideration, set boundaries
that are often relevant for optimizing compensation of the feed-
back loop. If the compensation of the current control signal, i.e.,
the COMP pin, is designed to promote a current response that is
from the perspective of the power converter, they have a digital
faster than the inductor current can slew, then when a step load is
characteristic when changing between two extremes, and also
applied, the control signal will tend to initially respond in excess
because such fast slew rates tend to characterize modern digital (of the actual current change that is occurring) and then allow an
circuits, which often feature power management interrupts, i.e., overshoot of the current and output voltage since it is delayed in
interrupt signals used to turn circuitry on and off as needed during correcting its excess.
normal system operation. Optimally compensating a digital load For conventional loads, the following describes how the fre-
is more a task of impedance matching and dc gain determina-
quency corners (poles and zeros) are positioned or should be
tion than a task of ac loop optimization.
chosen to optimize the loop gain, beginning in the low
frequency spectrum:
REV. C
–11–
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