ADNS-2610 Просмотр технического описания (PDF) - Avago Technologies
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ADNS-2610 Datasheet PDF : 27 Pages
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Power-down Mode (PD) and Timing
ADNS-2610 can be placed in a power-down mode by
setting bit 6 in the configuration register via a serial I/O
port write operation. Note that while writing a “1” to bit
6 of the configuration register, all other bits must be writ-
ten with their original value in order to keep the current
configuration. After setting the configuration register,
wait at least 32 system clock cycles. To get the chip out
of the power-down mode, clear bit 6 in the configuration
register via a serial I/O port write operation. (CAUTION! In
power-down mode, the SPI timeout (t ) SPTT will not func-
tion. Therefore, no partial SPI command should be sent.
Otherwise, the sensor may go into a hang-up state). While
the sensor is in power-down mode, only the bit 6 data will
be written to the configuration register. Writing the other
configuration register values will not have any effect. For
an accurate report after power-up, wait for a total period
of 50 ms before the microcontroller is able to issue any
write/read operation to the ADNS-2610. The sensor register
settings, prior to power-down mode, will remain during
power-down mode.
CLK
SCK
SDIO
1 A6 A5 A4 A3
IDD
Figure 12. Power-down timing.
32 clock cycles min
D5 D4 D3 D2 D1 D0
tPD
The address of the configuration register is 0000000.
Assume that the original content of the configuration
register is 0x00.
SCK
SDIO
Write
Operation
1
0
Configuration Register Address
0
0
00
0
00
Configuration Register Data
1
00
00
00
Figure 13. Power-down configuration register writing operation.
Setting the power down bit simply sets the analog circuitry
into a no current state.
Note: LED_CNTL, and SDIO will be tri-stated during power
down mode.
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