DINx
DOUTx–
DOUTx+
tPLHD
VOD
tPHLD
3V
1.5V
0V
VOH
0V (DIFFERENTIAL)
VOL
VDIFF
VDIFF = DOUTx+ – DOUTx–
80%
0V
20%
tTLH
tTHL
Figure 4. Driver Propagation Delay and Transition Time Waveforms
VCC
VCC
DINx
S1
EN
SIGNAL
GENERATOR
50Ω
EN
DOUTx+
CL 50Ω
1.2V
50Ω
DOUTx–
CL
NOTES
1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
2. S1 CONNECTED TO VCC FOR tPHZ AND tPZH TEST.
3. S1 CONNECTED TO GND FOR tPLZ AND tPZL TEST.
Figure 5. Test Circuit for Driver Three-State Delay
EN WITH EN = GND
OR OPEN CIRCUIT
EN WITH EN = VCC
DOUTx+ WITH DINx = VCC
OR DOUTx– WITH DINx = GND
tPHZ
tPZH
DOUTx+ WITH DINx = GND
OR DOUTx– WITH DINx = VCC
tPLZ
tPZL
Figure 6. Driver Three-State Delay Waveforms
3V
1.5V
0V
3V
1.5V
0V
VOH
50%
1.2V
1.2V
50%
VOL
Rev. 0 | Page 5 of 12
ADN4665