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ADN4662

Single, 3 V, CMOS, LVDS Differential Line Receiver

Analog Devices 

Data Sheet

FEATURES

±15 kV ESD protection on input pins

400 Mbps (200 MHz) switching rates

Flow-through pinout simplifies PCB layout

2.5 ns maximum propagation delay

3.3 V power supply

High impedance outputs on power-down

Low power design: typically 18 mW (quiescent)

Interoperable with existing 5 V LVDS drivers

Accepts small swing (310 mV typical) differential signal

levels

Supports open, short, and terminated input fail-safe

0 V to −100 mV threshold region

Conforms to TIA/EIA-644 LVDS standard

Industrial operating temperature range: −40°C to +85°C

Available in surface-mount (SOIC) package

APPLICATIONS

Point-to-point data transmission

Multidrop buses

Clock distribution networks

Backplane receivers

GENERAL DESCRIPTION

The ADN4662 is a single, CMOS, low voltage differential

signaling (LVDS) line receiver offering data rates of over

400 Mbps (200 MHz), and ultralow power consumption.

It features a flow-through pinout for easy PCB layout and

separation of input and output signals.

The device accepts low voltage (310 mV typical) differential

input signals and converts them to a single-ended 3 V TTL/

CMOS logic level.

Single, 3 V, CMOS, LVDS

Differential Line Receiver

ADN4662

FUNCTIONAL BLOCK DIAGRAM

VCC

ADN4662

RIN+

RIN–

ROUT

NC GND NC NC

Figure 1.

The ADN4662 and its companion driver, the ADN4661, offer a

new solution to high speed, point-to-point data transmission,

and a low power alternative to emitter-coupled logic (ECL) or

positive emitter-coupled logic (PECL).

Rev. A

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