ADN2890(Rev0) Просмотр технического описания (PDF) - Analog Devices
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ADN2890 Datasheet PDF : 12 Pages
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ADN2890
PCB Layout
Figure 9 shows a recommended PC board layout. Use of 50 Ω
transmission lines is required for all high frequency input and
output signals to minimize reflections: PIN, NIN, OUTP and
OUTN. It is also necessary for the PIN/NIN input traces to be
matched in length, and OUTP/OUTN output traces to be
matched in length to avoid skew between the differential traces.
C1, C2, C3, and C4 are ac-coupling capacitors in series with the
high speed I/O. It is recommended that components be used
such that the pad for the capacitor is the same width as the
transmission line in order to minimize the mismatch in the 50
Ω transmission line at the capacitor’s pads. It is recommended
that the transmission lines not change layers through vias, if
possible. For supply decoupling, the 1 nF decoupling capacitor
should be placed on the same layer as the ADN2890 as close as
possible to the VCC pin. The 0.1 µF capacitor can be placed on
the bottom of the PCB directly underneath the 1 nF decoupling
capacitor. All high speed CML outputs are back-terminated on
chip with 50 Ω resistors connected between the output pin and
VCC. The high speed inputs, PIN and NIN, are internally
terminated with 50 Ω to an internal reference voltage.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
Soldering Guidelines for Chip Scale Package
The lands on the 16 LFCSP are rectangular. The printed circuit
board pad for these should be 0.1 mm longer than the package
land length and 0.05 mm wider than the package land width.
The land should be centered on the pad. This ensures that the
solder joint size is maximized. The bottom of the chip scale
package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to VEE using filled vias so
that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
TO ROSA
PLACE C5 ON
BOTTOM OF BOARD
UNDERNEATH C6
C1
C6
PIN
∼4mm
NIN
C2
R1, C9, C10 ON BOTTOM
1 EXPOSED PAD
VIAS TO
GND
DOUBLE-VIAS TO REDUCE
INDUCTANCE TO SUPPLY
AND GND
PLACE C7 ON
BOTTOM OF BOARD
UNDERNEATH C8
C8
C3
OUTP
OUTN
C4
DOUBLE-VIA TO GND
TO REDUCE INDUCTANCE
VIA TO C12, R2
ON BOTTOM
C11
VIA TO BOTTOM
Figure 9. Recommended ADN2890 PCB Layout
Rev. 0 | Page 10 of 12
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