ADN2860(RevB) Просмотр технического описания (PDF) - Analog Devices
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производитель
ADN2860 Datasheet PDF : 20 Pages
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ADN2860
Parameter
Input Leakage Current (Excluding WP
and A0)
Input Capacitance5
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Symbol
II
CI
VDD
VDD/VSS
IDD
ISS
EEMEM Data Storing Mode Current
EEMEM Data Restoring Mode Current
Power Dissipation7
Power Supply Sensitivity5
IDD_STORE
IDD_RESTORE
PDISS
PSS
Conditions
Min
VIN = 0 V or VDD
VSS = 0 V
VIH = VDD or VIL = GND, VSS = 0 V
VIH = VDD or VIL = GND, VDD =
2.5 V, VSS = −2.5 V
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD = 5 V or VIL = GND
∆VDD = 5 V ± 10%
2.7
±2.25
Typ1 Max
Unit
±1
μA
5
pF
5.5
V
±2.75 V
5
15
μA
−5
−15
μA
35
mA
2.5
mA
25
75
μW
0.01
0.025 %/%
1 Typical represents average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
t8
SDA
t1
t8
t9
t6
SCL
t2
P
S
t3
t4
t5
t7
S
Figure 2. I2C Timing Diagram
t10
P
Rev. B | Page 4 of 20
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